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| author | Suman Anna <s-anna@ti.com> | 2017-01-11 19:22:17 -0600 |
|---|---|---|
| committer | Philipp Zabel <p.zabel@pengutronix.de> | 2017-01-12 11:13:54 +0100 |
| commit | 17ee33072af1f320a617a2447fa9548de41d5698 (patch) | |
| tree | b30132353abe347f203d2facc52fe1963f5357eb /Documentation/devicetree/bindings/reset | |
| parent | 1013258814bd396964cfcedc8fc590c9098266b3 (diff) | |
| download | linux-stable-17ee33072af1f320a617a2447fa9548de41d5698.tar.gz linux-stable-17ee33072af1f320a617a2447fa9548de41d5698.tar.bz2 linux-stable-17ee33072af1f320a617a2447fa9548de41d5698.zip | |
Documentation: dt: reset: Revise typos in TI syscon reset example
Fix couple of typos in the example given in the TI syscon reset
binding. The ti,reset-bits used for DSP0 are corrected to match
the values that will be used in the actual DT node.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'Documentation/devicetree/bindings/reset')
| -rw-r--r-- | Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt index 164c7f34c451..c516d24959f2 100644 --- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt +++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt @@ -63,7 +63,7 @@ Example: -------- The following example demonstrates a syscon node, the reset controller node using the syscon node, and a consumer (a DSP device) on the TI Keystone 2 -Edison SoC. +66AK2E SoC. / { soc { @@ -71,13 +71,13 @@ Edison SoC. compatible = "syscon", "simple-mfd"; reg = <0x02350000 0x1000>; - pscrst: psc-reset { + pscrst: reset-controller { compatible = "ti,k2e-pscrst", "ti,syscon-reset"; #reset-cells = <1>; ti,reset-bits = < - 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_SET|DEASSERT_CLEAR|STATUS_SET) /* 0: pcrst-dsp0 */ - 0xa40 5 0xa44 3 0 0 (ASSERT_SET|DEASSERT_CLEAR|STATUS_NONE) /* 1: pcrst-example */ + 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ + 0xa40 5 0xa44 3 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE) /* 1: example */ >; }; }; |