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| author | Marek Vasut <marex@denx.de> | 2023-02-19 15:22:50 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-03-09 17:12:10 +0100 |
| commit | 872eb918d8e10a6293240e0dd89a45842079c03c (patch) | |
| tree | 3bf1f8b1df03231800ff676c4823acc8d75bbd07 /Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml | |
| parent | cf8d4027a748b713d239cedaa77193e2e60b8811 (diff) | |
| download | linux-stable-872eb918d8e10a6293240e0dd89a45842079c03c.tar.gz linux-stable-872eb918d8e10a6293240e0dd89a45842079c03c.tar.bz2 linux-stable-872eb918d8e10a6293240e0dd89a45842079c03c.zip | |
dt-bindings: serial: imx: Document mandatory clock properties
The UART IP must be connected to clock, document the properties in DT bindings.
Update example to match Linux arch/arm/boot/dts/imx51.dtsi .
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230219142250.10176-2-marex@denx.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml b/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml index c22aab8c55f8..40414247d61a 100644 --- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml @@ -49,6 +49,14 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 2 + + clock-names: + items: + - const: ipg + - const: per + dmas: items: - description: DMA controller phandle and request line for RX @@ -96,12 +104,16 @@ properties: required: - compatible - reg + - clocks + - clock-names - interrupts unevaluatedProperties: false examples: - | + #include <dt-bindings/clock/imx5-clock.h> + aliases { serial0 = &uart1; }; @@ -110,6 +122,9 @@ examples: compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fbc000 0x4000>; interrupts = <31>; + clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, + <&clks IMX5_CLK_UART1_PER_GATE>; + clock-names = "ipg", "per"; dmas = <&sdma 18 4 1>, <&sdma 19 4 2>; dma-names = "rx", "tx"; uart-has-rtscts; |