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authorConor Dooley <conor.dooley@microchip.com>2023-06-07 21:28:30 +0100
committerPalmer Dabbelt <palmer@rivosinc.com>2023-06-21 07:45:18 -0700
commit1e5cae98e46d15f4dc7c675e1bd0ed2172ea181c (patch)
tree004ede69685f51eb90545dbdb236de98e104bbcb /Documentation/devicetree
parent7816ebc1ddd16b5cc95febb75f778bf88411a365 (diff)
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dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support
Similar to commit 41ebfc91f785 ("dt-bindings: riscv: explicitly mention assumption of Zicsr & Zifencei support"), the Zicntr and Zihpm extensions also used to be part of the base ISA but were removed after the bindings were merged. Document the assumption of their presence in the base ISA. Suggested-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230607-rerun-retinal-5e8ba89e98f1@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/riscv/cpus.yaml4
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index db5253a2a74a..d5208881a1fb 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -89,8 +89,8 @@ properties:
Due to revisions of the ISA specification, some deviations
have arisen over time.
Notably, riscv,isa was defined prior to the creation of the
- Zicsr and Zifencei extensions and thus "i" implies
- "zicsr_zifencei".
+ Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"
+ implies "zicntr_zicsr_zifencei_zihpm".
While the isa strings in ISA specification are case
insensitive, letters in the riscv,isa string must be all