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| author | Palmer Dabbelt <palmer@rivosinc.com> | 2023-06-22 14:23:56 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-06-23 10:06:23 -0700 |
| commit | 488833ccdcac118da16701f4ee0673b20ba47fe3 (patch) | |
| tree | ae2d46b358e0784480ce3be6225980dbe95abb9b /Documentation/devicetree | |
| parent | 91afbaafd6b1f1846520efd2b158066a25a1a316 (diff) | |
| parent | 1ffe6ddc5c64f88b1ec2e250327defb5446a7904 (diff) | |
| download | linux-stable-488833ccdcac118da16701f4ee0673b20ba47fe3.tar.gz linux-stable-488833ccdcac118da16701f4ee0673b20ba47fe3.tar.bz2 linux-stable-488833ccdcac118da16701f4ee0673b20ba47fe3.zip | |
Merge patch series "dt-bindings: riscv: cpus: switch to unevaluatedProperties: false"
Conor Dooley <conor@kernel.org> says:
From: Conor Dooley <conor.dooley@microchip.com>
Do the various bits needed to drop the additionalProperties: true that
we currently have in riscv/cpu.yaml, to permit actually enforcing what
people put in cpus nodes.
* b4-shazam-merge:
dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
dt-bindings: riscv: cpus: add a ref the common cpu schema
Link: https://lore.kernel.org/r/20230615-creamer-emu-ade0fa0bdb68@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c2ed979c9428..67bd239ead0b 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -23,6 +23,9 @@ description: | two cores, each of which has two hyperthreads, could be described as having four harts. +allOf: + - $ref: /schemas/cpu.yaml# + properties: compatible: oneOf: @@ -98,6 +101,9 @@ properties: $ref: /schemas/types.yaml#/definitions/string pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + # RISC-V has multiple properties for cache op block sizes as the sizes + # differ between individual CBO extensions + cache-op-block-size: false # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false @@ -137,7 +143,7 @@ required: - riscv,isa - interrupt-controller -additionalProperties: true +unevaluatedProperties: false examples: - | |