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| author | Damien Le Moal <damien.lemoal@wdc.com> | 2021-02-10 14:02:18 +0900 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2021-02-22 17:51:08 -0800 |
| commit | 90ddcd642a41b72498817da9dd21ed09d6e4f8e0 (patch) | |
| tree | bc3cc14abf703e7c6cfe2dd478b5283e5f345202 /Documentation/devicetree | |
| parent | 7ef71c719eb462edaa6078405654d2447c7a5488 (diff) | |
| download | linux-stable-90ddcd642a41b72498817da9dd21ed09d6e4f8e0.tar.gz linux-stable-90ddcd642a41b72498817da9dd21ed09d6e4f8e0.tar.bz2 linux-stable-90ddcd642a41b72498817da9dd21ed09d6e4f8e0.zip | |
dt-bindings: update sifive plic compatible string
Add the compatible string "canaan,k210-plic" to the Sifive plic bindings
to indicate the use of the "sifive,plic-1.0.0" IP block in the Canaan
Kendryte K210 SoC. The description is also updated to reflect this
change, that is, that SoCs from other vendors may also use this plic
implementation.
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index b9a61c9f7530..08d5a57ce00f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SiFive Platform-Level Interrupt Controller (PLIC) description: - SiFive SOCs include an implementation of the Platform-Level Interrupt Controller - (PLIC) high-level specification in the RISC-V Privileged Architecture - specification. The PLIC connects all external interrupts in the system to all - hart contexts in the system, via the external interrupt source in each hart. + SiFive SoCs and other RISC-V SoCs include an implementation of the + Platform-Level Interrupt Controller (PLIC) high-level specification in + the RISC-V Privileged Architecture specification. The PLIC connects all + external interrupts in the system to all hart contexts in the system, via + the external interrupt source in each hart. A hart context is a privilege mode in a hardware execution thread. For example, in an 4 core system with 2-way SMT, you have 8 harts and probably at least two @@ -42,7 +43,9 @@ maintainers: properties: compatible: items: - - const: sifive,fu540-c000-plic + - enum: + - sifive,fu540-c000-plic + - canaan,k210-plic - const: sifive,plic-1.0.0 reg: |