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| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-06-09 16:07:06 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-06-19 09:28:00 -0700 |
| commit | f20233852ae295fde59c9a28c4a2087d693de3fb (patch) | |
| tree | 66fa19c4c4651a508d8731eb18f8a6fbb3593f2b /Documentation/devicetree | |
| parent | ca7473cb8312232d8e03808004c54528e9446b73 (diff) | |
| download | linux-stable-f20233852ae295fde59c9a28c4a2087d693de3fb.tar.gz linux-stable-f20233852ae295fde59c9a28c4a2087d693de3fb.tar.bz2 linux-stable-f20233852ae295fde59c9a28c4a2087d693de3fb.zip | |
dt-bindings: riscv: cpus: drop unneeded quotes
Cleanup bindings dropping unneeded quotes. Once all these are fixed,
checking for this can be enabled in yamllint.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230609140706.64623-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index db5253a2a74a..8a56473cdd5a 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -61,7 +61,7 @@ properties: hart. These values originate from the RISC-V Privileged Specification document, available from https://riscv.org/specifications/ - $ref: "/schemas/types.yaml#/definitions/string" + $ref: /schemas/types.yaml#/definitions/string enum: - riscv,sv32 - riscv,sv39 @@ -95,7 +95,7 @@ properties: While the isa strings in ISA specification are case insensitive, letters in the riscv,isa string must be all lowercase. - $ref: "/schemas/types.yaml#/definitions/string" + $ref: /schemas/types.yaml#/definitions/string pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here @@ -120,7 +120,7 @@ properties: - interrupt-controller cpu-idle-states: - $ref: '/schemas/types.yaml#/definitions/phandle-array' + $ref: /schemas/types.yaml#/definitions/phandle-array items: maxItems: 1 description: | |