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| author | Matt Roper <matthew.d.roper@intel.com> | 2021-07-28 22:41:18 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-08-10 15:42:49 -0700 |
| commit | 5c5c40e28c52a36bb5ac26817275d5a0281ab819 (patch) | |
| tree | 583c9602578d4694b3ff9d747a3e23ce13d391b2 /Documentation/gpu | |
| parent | 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5 (diff) | |
| download | linux-stable-5c5c40e28c52a36bb5ac26817275d5a0281ab819.tar.gz linux-stable-5c5c40e28c52a36bb5ac26817275d5a0281ab819.tar.bz2 linux-stable-5c5c40e28c52a36bb5ac26817275d5a0281ab819.zip | |
drm/i915/xehp: Xe_HP shadowed registers are a strict superset of gen12
The list of shadowed registers on XeHP is identical to the set for
earlier gen12 platforms, with additional ranges added for the new VCS
and VECS engines. Since those register ranges were reserved on earlier
gen12 platforms, it's safe to consolidate to a single gen12 table
rather than tracking Xe_HP separately.
Bspec: 52077
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Caz Yokoyama <caz.yokoyama@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210729054118.2458523-7-matthew.d.roper@intel.com
Diffstat (limited to 'Documentation/gpu')
0 files changed, 0 insertions, 0 deletions