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author | Jochen Friedrich <jochen@scram.de> | 2008-07-05 13:29:28 +0200 |
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committer | Kumar Gala <galak@kernel.crashing.org> | 2008-07-16 17:57:40 -0500 |
commit | ade254d7f05cb74ab0a951ab105bc9ae872f045e (patch) | |
tree | 7543d4f28d59c57c633a5d521d1c13708f591cb7 /Documentation/powerpc | |
parent | 89ae5b2b9357cd715ab25df50e5fa56ae30aaf80 (diff) | |
download | linux-stable-ade254d7f05cb74ab0a951ab105bc9ae872f045e.tar.gz linux-stable-ade254d7f05cb74ab0a951ab105bc9ae872f045e.tar.bz2 linux-stable-ade254d7f05cb74ab0a951ab105bc9ae872f045e.zip |
powerpc: Add documentation for CPM GPIO banks
Signed-off-by: Jochen Friedrich <jochen@scram.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'Documentation/powerpc')
-rw-r--r-- | Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt new file mode 100644 index 000000000000..1815dfede1bc --- /dev/null +++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt @@ -0,0 +1,38 @@ +Every GPIO controller node must have #gpio-cells property defined, +this information will be used to translate gpio-specifiers. + +On CPM1 devices, all ports are using slightly different register layouts. +Ports A, C and D are 16bit ports and Ports B and E are 32bit ports. + +On CPM2 devices, all ports are 32bit ports and use a common register layout. + +Required properties: +- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b", + "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d", + "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank" +- #gpio-cells : Should be two. The first cell is the pin number and the + second cell is used to specify optional paramters (currently unused). +- gpio-controller : Marks the port as GPIO controller. + +Example of three SOC GPIO banks defined as gpio-controller nodes: + + CPM1_PIO_A: gpio-controller@950 { + #gpio-cells = <2>; + compatible = "fsl,cpm1-pario-bank-a"; + reg = <0x950 0x10>; + gpio-controller; + }; + + CPM1_PIO_B: gpio-controller@ab8 { + #gpio-cells = <2>; + compatible = "fsl,cpm1-pario-bank-b"; + reg = <0xab8 0x10>; + gpio-controller; + }; + + CPM1_PIO_E: gpio-controller@ac8 { + #gpio-cells = <2>; + compatible = "fsl,cpm1-pario-bank-e"; + reg = <0xac8 0x18>; + gpio-controller; + }; |