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| author | Evan Green <evan@rivosinc.com> | 2023-05-09 11:25:03 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-06-19 09:53:10 -0700 |
| commit | c0baf321038d5fa4273c0dc495d78f39848dd8fc (patch) | |
| tree | 27ac91fb3521ca72078e3d0d5b908772dd0ebd29 /Documentation/riscv | |
| parent | 82e9c66e81c814e20ee2a3aafb60a9012c79fb40 (diff) | |
| download | linux-stable-c0baf321038d5fa4273c0dc495d78f39848dd8fc.tar.gz linux-stable-c0baf321038d5fa4273c0dc495d78f39848dd8fc.tar.bz2 linux-stable-c0baf321038d5fa4273c0dc495d78f39848dd8fc.zip | |
RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
Add two new bits to the IMA_EXT_0 key for ZBA, ZBB, and ZBS extensions.
These are accurately reported per CPU.
Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Link: https://lore.kernel.org/r/20230509182504.2997252-4-evan@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/riscv')
| -rw-r--r-- | Documentation/riscv/hwprobe.rst | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 9f0dd62dcb5d..fb25670ef0e5 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -64,6 +64,16 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is + supported, as defined in version 1.0 of the Bit-Manipulation ISA + extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined + in version 1.0 of the Bit-Manipulation ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined + in version 1.0 of the Bit-Manipulation ISA extensions. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. |