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| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-02-24 10:12:34 +0100 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2024-04-03 08:13:32 -0500 |
| commit | 438d3fc46f0deba24da7ded046c818e7bf434d24 (patch) | |
| tree | 5ac5e7ef6dd1b1632017da093edf7dcfa83b5661 /Documentation | |
| parent | a1aa5390cc912934fee76ce80af5f940452fa987 (diff) | |
| download | linux-stable-438d3fc46f0deba24da7ded046c818e7bf434d24.tar.gz linux-stable-438d3fc46f0deba24da7ded046c818e7bf434d24.tar.bz2 linux-stable-438d3fc46f0deba24da7ded046c818e7bf434d24.zip | |
dt-bindings: clock: keystone: remove unstable remark
Keystone clock controller bindings were marked as work-in-progress /
unstable in 2013 in commit b9e0d40c0d83 ("clk: keystone: add Keystone
PLL clock driver") and commit 7affe5685c96 ("clk: keystone: Add gate
control clock driver") Almost eleven years is enough, so drop the
"unstable" remark and expect usual ABI rules.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240224091236.10146-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/keystone-gate.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/clock/keystone-pll.txt | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/clock/keystone-gate.txt b/Documentation/devicetree/bindings/clock/keystone-gate.txt index c5aa187026e3..43f6fb6c9392 100644 --- a/Documentation/devicetree/bindings/clock/keystone-gate.txt +++ b/Documentation/devicetree/bindings/clock/keystone-gate.txt @@ -1,5 +1,3 @@ -Status: Unstable - ABI compatibility may be broken in the future - Binding for Keystone gate control driver which uses PSC controller IP. This binding uses the common clock binding[1]. diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt index 9a3fbc665606..69b0eb7c03c9 100644 --- a/Documentation/devicetree/bindings/clock/keystone-pll.txt +++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt @@ -1,5 +1,3 @@ -Status: Unstable - ABI compatibility may be broken in the future - Binding for keystone PLLs. The main PLL IP typically has a multiplier, a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where as the Main |