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authorLinus Torvalds <torvalds@linux-foundation.org>2023-09-29 08:55:21 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2023-09-29 08:55:21 -0700
commitacfdcaeed6e6b954f5b99210b8f05cbc18200945 (patch)
tree153f54c5ecc4e46e07cea0c5b6bf664bf63cf221 /Documentation
parent94b7ed384fa9d397ff0aabff76a8de2f7e107144 (diff)
parenta47b44fbb13f5e7a981b4515dcddc93a321ae89c (diff)
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd: "A bunch of clk driver fixes for issues found recently: - Fix the binding for versaclock3 that was introduced this merge window so we know what the values are for clk consumers - Fix a 64-bit division issue in the versaclock3 driver - Avoid breakage in the versaclock3 driver by rejiggering the enums used to layout clks - Fix the parent name of a clk in the Spreadtrum ums512 clk driver - Fix a suspend/resume issue in Skyworks Si521xx clk driver where regmap restoration fails because writes are wedged - Return zero from Tegra bpmp recalc_rate() implementation when an error occurs so we don't consider an error as a large rate" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: tegra: fix error return case for recalc_rate clk: si521xx: Fix regmap write accessor clk: si521xx: Use REGCACHE_FLAT instead of NONE clk: sprd: Fix thm_parents incorrect configuration clk: vc3: Make vc3_clk_mux enum values based on vc3_clk enum values clk: vc3: Fix output clock mapping clk: vc3: Fix 64 by 64 division dt-bindings: clock: versaclock3: Add description for #clock-cells property
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,5p35023.yaml11
1 files changed, 7 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
index 839648e753d4..42b6f80613f3 100644
--- a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
@@ -37,6 +37,9 @@ properties:
maxItems: 1
'#clock-cells':
+ description:
+ The index in the assigned-clocks is mapped to the output clock as below
+ 0 - REF, 1 - SE1, 2 - SE2, 3 - SE3, 4 - DIFF1, 5 - DIFF2.
const: 1
clocks:
@@ -68,7 +71,7 @@ examples:
reg = <0x68>;
#clock-cells = <1>;
- clocks = <&x1_x2>;
+ clocks = <&x1>;
renesas,settings = [
80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
@@ -79,8 +82,8 @@ examples:
assigned-clocks = <&versa3 0>, <&versa3 1>,
<&versa3 2>, <&versa3 3>,
<&versa3 4>, <&versa3 5>;
- assigned-clock-rates = <12288000>, <25000000>,
- <12000000>, <11289600>,
- <11289600>, <24000000>;
+ assigned-clock-rates = <24000000>, <11289600>,
+ <11289600>, <12000000>,
+ <25000000>, <12288000>;
};
};