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author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-05-22 09:14:03 +0200 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-05-22 09:14:03 +0200 |
commit | c9cf27d9dee20193660b6582e4e6d6b315bff217 (patch) | |
tree | 5fadc863352bec51f86dd978953249920c67792b /Documentation | |
parent | f37d13d52c0560bd2bac40b22466af538e61a5ce (diff) | |
parent | b35da2e86f256a3a4be7c3b31507016100b00847 (diff) | |
download | linux-stable-c9cf27d9dee20193660b6582e4e6d6b315bff217.tar.gz linux-stable-c9cf27d9dee20193660b6582e4e6d6b315bff217.tar.bz2 linux-stable-c9cf27d9dee20193660b6582e4e6d6b315bff217.zip |
Merge tag 'icc-5.8-rc1' of https://git.linaro.org/people/georgi.djakov/linux into char-misc-next
Georgi writes:
interconnect changes for 5.8
These are the interconnect changes for the 5.8-rc1 merge window:
Core changes:
- Convert the framework core from tristate to bool to make handling
dependencies between other core frameworks easier
- Add of_icc_get_by_index()
- Add devm_of_icc_get() helper function
- Add icc_enable() and icc_disable() helpers
New drivers:
- Platform driver for NXP i.MX8MM SoC
- Platform driver for NXP i.MX8MN SoC
- Platform driver for NXP i.MX8MQ SoC
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
* tag 'icc-5.8-rc1' of https://git.linaro.org/people/georgi.djakov/linux:
interconnect: Remove unused module exit code from core
interconnect: Disallow interconnect core to be built as a module
interconnect: Add of_icc_get_by_index() helper function
interconnect: Add helpers for enabling/disabling a path
interconnect: imx: Fix return value check in imx_icc_node_init_qos()
interconnect: imx: Add platform driver for imx8mn
interconnect: imx: Add platform driver for imx8mq
interconnect: imx: Add platform driver for imx8mm
interconnect: Add imx core driver
dt-bindings: interconnect: Add bindings for imx8m noc
interconnect: Add devm_of_icc_get() as exported API for users
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml new file mode 100644 index 000000000000..ff09550ad959 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic i.MX bus frequency device + +maintainers: + - Leonard Crestez <leonard.crestez@nxp.com> + +description: | + The i.MX SoC family has multiple buses for which clock frequency (and + sometimes voltage) can be adjusted. + + Some of those buses expose register areas mentioned in the memory maps as GPV + ("Global Programmers View") but not all. Access to this area might be denied + for normal (non-secure) world. + + The buses are based on externally licensed IPs such as ARM NIC-301 and + Arteris FlexNOC but DT bindings are specific to the integration of these bus + interconnect IPs into imx SOCs. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx8mn-nic + - fsl,imx8mm-nic + - fsl,imx8mq-nic + - const: fsl,imx8m-nic + - items: + - enum: + - fsl,imx8mn-noc + - fsl,imx8mm-noc + - fsl,imx8mq-noc + - const: fsl,imx8m-noc + - const: fsl,imx8m-nic + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + operating-points-v2: true + opp-table: true + + fsl,ddrc: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: + Phandle to DDR Controller. + + '#interconnect-cells': + description: + If specified then also act as an interconnect provider. Should only be + set once per soc on the main noc. + const: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mm-clock.h> + #include <dt-bindings/interconnect/imx8mm.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + noc: interconnect@32700000 { + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MM_CLK_NOC>; + #interconnect-cells = <1>; + fsl,ddrc = <&ddrc>; + + operating-points-v2 = <&noc_opp_table>; + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133M { + opp-hz = /bits/ 64 <133333333>; + }; + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; + }; + + ddrc: memory-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, + <&clk IMX8MM_DRAM_PLL>, + <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>; + }; |