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authorJohn Crispin <blogic@openwrt.org>2012-07-11 16:33:43 +0200
committerJohn Crispin <blogic@openwrt.org>2012-09-13 10:31:00 +0200
commitc9e854cf940fbc09846c255895efceb3bc9bf095 (patch)
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GPIO: MIPS: lantiq: fix overflow inside stp-xway driver
The driver was using a 16 bit field for storing the shadow value of the shift register cascade. This resulted in only the first 2 shift registeres receiving the correct data. The third shift register would always receive 0x00. Fix this by using a 32bit field for the shadow value. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-kernel@vger.kernel.org
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