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| author | Vignesh Raghavendra <vigneshr@ti.com> | 2019-12-05 12:29:34 +0530 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-12-23 19:13:00 +0200 |
| commit | 7f412111e276bbc4cbf6064aa6a0c6df6b19a385 (patch) | |
| tree | 5e093301d7f32597e3f54427d3e3c420494c8c57 /README | |
| parent | bd8a6e31b87b39a03ab11820776363640440dbe0 (diff) | |
| download | linux-stable-7f412111e276bbc4cbf6064aa6a0c6df6b19a385.tar.gz linux-stable-7f412111e276bbc4cbf6064aa6a0c6df6b19a385.tar.bz2 linux-stable-7f412111e276bbc4cbf6064aa6a0c6df6b19a385.zip | |
mtd: spi-nor: Add entries for mt25q variants
Add entries for mt25q*256a and mt25q*512a flashes. These are similar to
existing n25q variants but support stateless 4 byte addressing opcodes
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'README')
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