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| author | Vineet Gupta <vgupta@kernel.org> | 2023-02-15 21:06:33 -0800 |
|---|---|---|
| committer | Vineet Gupta <vgupta@kernel.org> | 2023-12-08 16:30:24 -0800 |
| commit | 6732c0e494ac35fbadd749bbbd226c0aceb2d2c4 (patch) | |
| tree | de0ec244bb228891a3cc139a3fb8abd97b96a3b1 /arch/arc/mm/tlb.c | |
| parent | 3a02ec2f0b304af6b38e9cc5a009bf517d38e72c (diff) | |
| download | linux-stable-6732c0e494ac35fbadd749bbbd226c0aceb2d2c4.tar.gz linux-stable-6732c0e494ac35fbadd749bbbd226c0aceb2d2c4.tar.bz2 linux-stable-6732c0e494ac35fbadd749bbbd226c0aceb2d2c4.zip | |
ARC: mm: retire support for aliasing VIPT D$
Legacy ARC700 processors (first generation of MMU enabled ARC cores) had
VIPT cached which could be configured such that they could alias.
Corresponding support in kernel (with all the obnoxious cache flush overhead)
was added in ARC port 10 years ago to support 1 silicon. That is long bygone
and we can let it RIP.
Cc: Matthew Wilcox (Oracle) <willy@infradead.org>
Signed-off-by: Vineet Gupta <vgupta@kernel.org>
Diffstat (limited to 'arch/arc/mm/tlb.c')
| -rw-r--r-- | arch/arc/mm/tlb.c | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c index e536b2dcd4b0..ad702b49aeb3 100644 --- a/arch/arc/mm/tlb.c +++ b/arch/arc/mm/tlb.c @@ -478,21 +478,15 @@ void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma, create_tlb(vma, vaddr, ptep); - if (page == ZERO_PAGE(0)) { + if (page == ZERO_PAGE(0)) return; - } /* - * Exec page : Independent of aliasing/page-color considerations, - * since icache doesn't snoop dcache on ARC, any dirty - * K-mapping of a code page needs to be wback+inv so that - * icache fetch by userspace sees code correctly. - * !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it - * so userspace sees the right data. - * (Avoids the flush for Non-exec + congruent mapping case) + * For executable pages, since icache doesn't snoop dcache, any + * dirty K-mapping of a code page needs to be wback+inv so that + * icache fetch by userspace sees code correctly. */ - if ((vma->vm_flags & VM_EXEC) || - addr_not_cache_congruent(paddr, vaddr)) { + if (vma->vm_flags & VM_EXEC) { struct folio *folio = page_folio(page); int dirty = !test_and_set_bit(PG_dc_clean, &folio->flags); if (dirty) { |