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| author | Markus Niebel <Markus.Niebel@ew.tq-group.com> | 2021-11-22 12:37:40 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2021-12-06 08:51:14 +0800 |
| commit | ef3846247b41391434c23fcd9560daa57d14bb7a (patch) | |
| tree | 68feaf52ebebb00b1fec249f12535c8f0392c303 /arch/arm/boot/dts/imx6q-mba6.dtsi | |
| parent | 2439d70c52c51f991b00b0ae5644e96033bd8165 (diff) | |
| download | linux-stable-ef3846247b41391434c23fcd9560daa57d14bb7a.tar.gz linux-stable-ef3846247b41391434c23fcd9560daa57d14bb7a.tar.bz2 linux-stable-ef3846247b41391434c23fcd9560daa57d14bb7a.zip | |
ARM: dts: imx6qdl: add TQ-Systems MBa6x device trees
Add device trees for the MBa6x mainboard with TQMa6Q/QP/DL SoMs.
As discussed, all new files are added with GPL-2.0-only license, as they
are too tightly intertwined with the SoC DTSIs imx6dl.dtsi and imx6q.dtsi,
which are GPL-2.0.
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q-mba6.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6q-mba6.dtsi | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q-mba6.dtsi b/arch/arm/boot/dts/imx6q-mba6.dtsi new file mode 100644 index 000000000000..0d7be4567291 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-mba6.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +&ecspi5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5_mba6x>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +}; + +ðphy { + rxdv-skew-ps = <180>; + txen-skew-ps = <120>; + rxd3-skew-ps = <180>; + rxd2-skew-ps = <180>; + rxd1-skew-ps = <180>; + rxd0-skew-ps = <180>; + txd3-skew-ps = <120>; + txd2-skew-ps = <0>; + txd1-skew-ps = <180>; + txd0-skew-ps = <360>; + txc-skew-ps = <1860>; + rxc-skew-ps = <1860>; +}; + +&sata { + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi5_mba6x: ecspi5grp-mba6x { + fsl,pins = < + /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b099 + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0xb099 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0xb099 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0xb099 /* eCSPI5 SS0 */ + >; + }; +}; |