ARM: dts: Move .dts files to vendor sub-directories

The arm dts directory has grown to 1559 boards which makes it a bit
unwieldy to maintain and use. Past attempts stalled out due to plans to
move .dts files out of the kernel tree. Doing that is no longer planned
(any time soon at least), so let's go ahead and group .dts files by
vendors. This move aligns arm with arm64 .dts file structure.

There's no change to dtbs_install as the flat structure is maintained on
install.

The naming of vendor directories is roughly in this order of preference:
- Matching original and current SoC vendor prefix/name (e.g. ti, qcom)
- Current vendor prefix/name if still actively sold (SoCs which have
  been aquired) (e.g. nxp/imx)
- Existing platform name for older platforms not sold/maintained by any
  company (e.g. gemini, nspire)

The whole move was scripted with the exception of MAINTAINERS and a few
makefile fixups.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Paul Barker <paul.barker@sancloud.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Nick Hawkins <nick.hawkins@hpe.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Peter Rosin <peda@axentia.se>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Romain Perier <romain.perier@gmail.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>

1 files changed, 0 insertions, 792 deletions

diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
deleted file mode 100644
index e2fe337f7d9e..000000000000
--- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi
+++ /dev/null
@@ -1,792 +0,0 @@
-/*
- * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/sound/fsl-imx-audmux.h>
-
-/ {
-	aliases {
-		can0 = &can2;
-		can1 = &can1;
-		ethernet0 = &fec;
-		lcdif-23bit-pins-a = &pinctrl_disp0_1;
-		lcdif-24bit-pins-a = &pinctrl_disp0_2;
-		pwm0 = &pwm1;
-		pwm1 = &pwm2;
-		reg-can-xcvr = &reg_can_xcvr;
-		stk5led = &user_led;
-		usbotg = &usbotg;
-		sdhc0 = &usdhc1;
-		sdhc1 = &usdhc2;
-	};
-
-	memory@10000000 {
-		device_type = "memory";
-		reg = <0x10000000 0>; /* will be filled by U-Boot */
-	};
-
-	clocks {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		mclk: clock@0 {
-			compatible = "fixed-clock";
-			reg = <0>;
-			#clock-cells = <0>;
-			clock-frequency = <26000000>;
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		power {
-			label = "Power Button";
-			gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
-			linux,code = <KEY_POWER>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		user_led: led-user {
-			label = "Heartbeat";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_user_led>;
-			gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-		};
-	};
-
-	reg_3v3_etn: regulator-3v3-etn {
-		compatible = "regulator-fixed";
-		regulator-name = "3V3_ETN";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_etnphy_power>;
-		gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	reg_2v5: regulator-2v5 {
-		compatible = "regulator-fixed";
-		regulator-name = "2V5";
-		regulator-min-microvolt = <2500000>;
-		regulator-max-microvolt = <2500000>;
-		regulator-always-on;
-	};
-
-	reg_3v3: regulator-3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "3V3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-	};
-
-	reg_can_xcvr: regulator-can-xcvr {
-		compatible = "regulator-fixed";
-		regulator-name = "CAN XCVR";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_flexcan_xcvr>;
-		gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
-	};
-
-	reg_lcd0_pwr: regulator-lcd0-pwr {
-		compatible = "regulator-fixed";
-		regulator-name = "LCD0 POWER";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_lcd0_pwr>;
-		gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-		status = "disabled";
-	};
-
-	reg_lcd1_pwr: regulator-lcd1-pwr {
-		compatible = "regulator-fixed";
-		regulator-name = "LCD1 POWER";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_lcd1_pwr>;
-		gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-		status = "disabled";
-	};
-
-	reg_usbh1_vbus: regulator-usbh1-vbus {
-		compatible = "regulator-fixed";
-		regulator-name = "usbh1_vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usbh1_vbus>;
-		gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	reg_usbotg_vbus: regulator-usbotg-vbus {
-		compatible = "regulator-fixed";
-		regulator-name = "usbotg_vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usbotg_vbus>;
-		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	sound {
-		compatible = "karo,imx6qdl-tx6-sgtl5000",
-			     "simple-audio-card";
-		simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_audmux>;
-		simple-audio-card,format = "i2s";
-		simple-audio-card,bitclock-master = <&codec_dai>;
-		simple-audio-card,frame-master = <&codec_dai>;
-		simple-audio-card,widgets =
-			"Microphone", "Mic Jack",
-			"Line", "Line In",
-			"Line", "Line Out",
-			"Headphone", "Headphone Jack";
-		simple-audio-card,routing =
-			"MIC_IN", "Mic Jack",
-			"Mic Jack", "Mic Bias",
-			"Headphone Jack", "HP_OUT";
-
-		cpu_dai: simple-audio-card,cpu {
-			sound-dai = <&ssi1>;
-		};
-
-		codec_dai: simple-audio-card,codec {
-			sound-dai = <&sgtl5000>;
-		};
-	};
-};
-
-&audmux {
-	status = "okay";
-
-	mux-ssi1 {
-		fsl,audmux-port = <0>;
-		fsl,port-config = <
-			(IMX_AUDMUX_V2_PTCR_SYN |
-			IMX_AUDMUX_V2_PTCR_TFSEL(4) |
-			IMX_AUDMUX_V2_PTCR_TCSEL(4) |
-			IMX_AUDMUX_V2_PTCR_TFSDIR |
-			IMX_AUDMUX_V2_PTCR_TCLKDIR)
-			IMX_AUDMUX_V2_PDCR_RXDSEL(4)
-		>;
-	};
-
-	mux-pins5 {
-		fsl,audmux-port = <4>;
-		fsl,port-config = <
-			IMX_AUDMUX_V2_PTCR_SYN
-			IMX_AUDMUX_V2_PDCR_RXDSEL(0)
-		>;
-	};
-};
-
-&can1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan1>;
-	xceiver-supply = <&reg_can_xcvr>;
-	status = "okay";
-};
-
-&can2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan2>;
-	xceiver-supply = <&reg_can_xcvr>;
-	status = "okay";
-};
-
-&ecspi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1>;
-	cs-gpios = <
-		&gpio2 30 GPIO_ACTIVE_HIGH
-		&gpio3 19 GPIO_ACTIVE_HIGH
-	>;
-	status = "disabled";
-};
-
-&fec {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>;
-	phy-mode = "rmii";
-	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
-	phy-reset-post-delay = <10>;
-	phy-handle = <&etnphy>;
-	phy-supply = <&reg_3v3_etn>;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		etnphy: ethernet-phy@0 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_etnphy_int>;
-			interrupt-parent = <&gpio7>;
-			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
-		};
-	};
-};
-
-&gpmi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
-	fsl,no-blockmark-swap;
-	status = "okay";
-};
-
-&i2c1 {
-	pinctrl-names = "default", "gpio";
-	pinctrl-0 = <&pinctrl_i2c1>;
-	pinctrl-1 = <&pinctrl_i2c1_gpio>;
-	scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
-	clock-frequency = <400000>;
-	status = "okay";
-
-	ds1339: rtc@68 {
-		compatible = "dallas,ds1339";
-		reg = <0x68>;
-		trickle-resistor-ohms = <250>;
-		trickle-diode-disable;
-	};
-};
-
-&i2c3 {
-	pinctrl-names = "default", "gpio";
-	pinctrl-0 = <&pinctrl_i2c3>;
-	pinctrl-1 = <&pinctrl_i2c3_gpio>;
-	scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
-	clock-frequency = <400000>;
-	status = "okay";
-
-	sgtl5000: sgtl5000@a {
-		compatible = "fsl,sgtl5000";
-		#sound-dai-cells = <0>;
-		reg = <0x0a>;
-		VDDA-supply = <&reg_2v5>;
-		VDDIO-supply = <&reg_3v3>;
-		clocks = <&mclk>;
-	};
-
-	polytouch: edt-ft5x06@38 {
-		compatible = "edt,edt-ft5x06";
-		reg = <0x38>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_edt_ft5x06>;
-		interrupt-parent = <&gpio6>;
-		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
-		reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
-		wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
-		wakeup-source;
-	};
-
-	touchscreen: tsc2007@48 {
-		compatible = "ti,tsc2007";
-		reg = <0x48>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_tsc2007>;
-		interrupt-parent = <&gpio3>;
-		interrupts = <26 0>;
-		gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
-		ti,x-plate-ohms = <660>;
-		wakeup-source;
-	};
-};
-
-&iomuxc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_hog>;
-
-	pinctrl_hog: hoggrp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x1b0b1 /* PWR BTN */
-		>;
-	};
-
-	pinctrl_audmux: audmuxgrp {
-		fsl,pins = <
-			MX6QDL_PAD_KEY_ROW1__AUD5_RXD		0x130b0 /* SSI1_RXD */
-			MX6QDL_PAD_KEY_ROW0__AUD5_TXD		0x110b0 /* SSI1_TXD */
-			MX6QDL_PAD_KEY_COL0__AUD5_TXC		0x130b0 /* SSI1_CLK */
-			MX6QDL_PAD_KEY_COL1__AUD5_TXFS		0x130b0 /* SSI1_FS */
-		>;
-	};
-
-	pinctrl_disp0_1: disp0grp-1 {
-		fsl,pins = <
-			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
-			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
-			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
-			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
-			/* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
-			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
-			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
-			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
-			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
-			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
-			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
-			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
-			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
-			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
-			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
-			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
-			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
-			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
-			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
-			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
-			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
-			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
-			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
-			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
-			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
-			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
-			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
-			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
-		>;
-	};
-
-	pinctrl_disp0_2: disp0grp-2 {
-		fsl,pins = <
-			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
-			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
-			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
-			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
-			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
-			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
-			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
-			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
-			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
-			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
-			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
-			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
-			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
-			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
-			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
-			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
-			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
-			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
-			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
-			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
-			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
-			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
-			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
-			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
-			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
-			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
-			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
-			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
-		>;
-	};
-
-	pinctrl_ecspi1: ecspi1grp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x0b0b0
-			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x0b0b0
-			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x0b0b0
-			MX6QDL_PAD_GPIO_19__ECSPI1_RDY		0x0b0b0
-			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x0b0b0 /* SPI CS0 */
-			MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x0b0b0 /* SPI CS1 */
-		>;
-	};
-
-	pinctrl_edt_ft5x06: edt-ft5x06grp {
-		fsl,pins = <
-			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x1b0b0 /* Interrupt */
-			MX6QDL_PAD_EIM_A16__GPIO2_IO22		0x1b0b0 /* Reset */
-			MX6QDL_PAD_EIM_A17__GPIO2_IO21		0x1b0b0 /* Wake */
-		>;
-	};
-
-	pinctrl_enet: enetgrp {
-		fsl,pins = <
-			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
-			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
-			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
-			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
-			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
-			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
-			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
-		>;
-	};
-
-	pinctrl_enet_mdio: enet-mdiogrp {
-		fsl,pins = <
-			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
-		>;
-	};
-
-	pinctrl_etnphy_int: etnphy-intgrp {
-		fsl,pins = <
-			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x1b0b1 /* ETN PHY INT */
-		>;
-	};
-
-	pinctrl_etnphy_power: etnphy-pwrgrp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D20__GPIO3_IO20		0x1b0b1 /* ETN PHY POWER */
-		>;
-	};
-
-	pinctrl_etnphy_rst: etnphy-rstgrp {
-		fsl,pins = <
-			MX6QDL_PAD_SD3_DAT2__GPIO7_IO06		0x1b0b1 /* ETN PHY RESET */
-		>;
-	};
-
-	pinctrl_flexcan1: flexcan1grp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX		0x1b0b0
-			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX		0x1b0b0
-		>;
-	};
-
-	pinctrl_flexcan2: flexcan2grp {
-		fsl,pins = <
-			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX	0x1b0b0
-			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX	0x1b0b0
-		>;
-	};
-
-	pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
-		fsl,pins = <
-			MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21	0x1b0b0 /* Flexcan XCVR enable */
-		>;
-	};
-
-	pinctrl_gpmi_nand: gpminandgrp {
-		fsl,pins = <
-			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0x0b0b1
-			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0x0b0b1
-			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0x0b0b1
-			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0x0b000
-			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0x0b0b1
-			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0x0b0b1
-			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0x0b0b1
-			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0x0b0b1
-			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0x0b0b1
-			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0x0b0b1
-			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0x0b0b1
-			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0x0b0b1
-			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0x0b0b1
-			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0x0b0b1
-			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0x0b0b1
-		>;
-	};
-
-	pinctrl_i2c1: i2c1grp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
-			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
-		>;
-	};
-
-	pinctrl_i2c1_gpio: i2c1-gpiogrp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D21__GPIO3_IO21		0x4001b8b1
-			MX6QDL_PAD_EIM_D28__GPIO3_IO28		0x4001b8b1
-		>;
-	};
-
-	pinctrl_i2c3: i2c3grp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
-			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
-		>;
-	};
-
-	pinctrl_i2c3_gpio: i2c3-gpiogrp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_3__GPIO1_IO03		0x4001b8b1
-			MX6QDL_PAD_GPIO_6__GPIO1_IO06		0x4001b8b1
-		>;
-	};
-
-	pinctrl_kpp: kppgrp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_9__KEY_COL6		0x1b0b1
-			MX6QDL_PAD_GPIO_4__KEY_COL7		0x1b0b1
-			MX6QDL_PAD_KEY_COL2__KEY_COL2		0x1b0b1
-			MX6QDL_PAD_KEY_COL3__KEY_COL3		0x1b0b1
-			MX6QDL_PAD_GPIO_2__KEY_ROW6		0x1b0b1
-			MX6QDL_PAD_GPIO_5__KEY_ROW7		0x1b0b1
-			MX6QDL_PAD_KEY_ROW2__KEY_ROW2		0x1b0b1
-			MX6QDL_PAD_KEY_ROW3__KEY_ROW3		0x1b0b1
-		>;
-	};
-
-	pinctrl_lcd0_pwr: lcd0-pwrgrp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x1b0b1 /* LCD Reset */
-		>;
-	};
-
-	pinctrl_lcd1_pwr: lcd-pwrgrp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_EB3__GPIO2_IO31		0x1b0b1 /* LCD Power Enable */
-		>;
-	};
-
-	pinctrl_pwm1: pwm1grp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_9__PWM1_OUT		0x1b0b1
-		>;
-	};
-
-	pinctrl_pwm2: pwm2grp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_1__PWM2_OUT		0x1b0b1
-		>;
-	};
-
-	pinctrl_tsc2007: tsc2007grp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0x1b0b0 /* Interrupt */
-		>;
-	};
-
-	pinctrl_uart1: uart1grp {
-		fsl,pins = <
-			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
-			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
-		>;
-	};
-
-	pinctrl_uart1_rtscts: uart1_rtsctsgrp {
-		fsl,pins = <
-			MX6QDL_PAD_SD3_DAT1__UART1_RTS_B	0x1b0b1
-			MX6QDL_PAD_SD3_DAT0__UART1_CTS_B	0x1b0b1
-		>;
-	};
-
-	pinctrl_uart2: uart2grp {
-		fsl,pins = <
-			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
-			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
-		>;
-	};
-
-	pinctrl_uart2_rtscts: uart2_rtsctsgrp {
-		fsl,pins = <
-			MX6QDL_PAD_SD4_DAT5__UART2_RTS_B	0x1b0b1
-			MX6QDL_PAD_SD4_DAT6__UART2_CTS_B	0x1b0b1
-		>;
-	};
-
-	pinctrl_uart3: uart3grp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
-			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
-		>;
-	};
-
-	pinctrl_uart3_rtscts: uart3_rtsctsgrp {
-		fsl,pins = <
-			MX6QDL_PAD_SD3_DAT3__UART3_CTS_B	0x1b0b1
-			MX6QDL_PAD_SD3_RST__UART3_RTS_B		0x1b0b1
-		>;
-	};
-
-	pinctrl_usbh1_vbus: usbh1-vbusgrp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x1b0b0 /* USBH1_VBUSEN */
-		>;
-	};
-
-	pinctrl_usbotg: usbotggrp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x17059
-		>;
-	};
-
-	pinctrl_usbotg_vbus: usbotg-vbusgrp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_7__GPIO1_IO07		0x1b0b0 /* USBOTG_VBUSEN */
-		>;
-	};
-
-	pinctrl_usdhc1: usdhc1grp {
-		fsl,pins = <
-			MX6QDL_PAD_SD1_CMD__SD1_CMD		0x070b1
-			MX6QDL_PAD_SD1_CLK__SD1_CLK		0x070b1
-			MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x070b1
-			MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x070b1
-			MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x070b1
-			MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x070b1
-			MX6QDL_PAD_SD3_CMD__GPIO7_IO02		0x170b0 /* SD1 CD */
-		>;
-	};
-
-	pinctrl_usdhc2: usdhc2grp {
-		fsl,pins = <
-			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x070b1
-			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x070b1
-			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x070b1
-			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x070b1
-			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x070b1
-			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x070b1
-			MX6QDL_PAD_SD3_CLK__GPIO7_IO03		0x170b0 /* SD2 CD */
-		>;
-	};
-
-	pinctrl_user_led: user-ledgrp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_A18__GPIO2_IO20		0x1b0b1 /* LED */
-		>;
-	};
-};
-
-&kpp {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_kpp>;
-	/* sample keymap */
-	/* row/col 0,1 are mapped to KPP row/col 6,7 */
-	linux,keymap = <
-		MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
-		MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
-		MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
-		MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
-		MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
-		MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
-		MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
-		MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
-		MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
-		MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
-		MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
-	>;
-	status = "okay";
-};
-
-&pwm1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm1>;
-	status = "disabled";
-};
-
-&pwm2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm2>;
-	status = "okay";
-};
-
-&ssi1 {
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
-	uart-has-rtscts;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
-	uart-has-rtscts;
-	status = "okay";
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
-	uart-has-rtscts;
-	status = "okay";
-};
-
-&usbh1 {
-	vbus-supply = <&reg_usbh1_vbus>;
-	dr_mode = "host";
-	disable-over-current;
-	status = "okay";
-};
-
-&usbotg {
-	vbus-supply = <&reg_usbotg_vbus>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usbotg>;
-	dr_mode = "peripheral";
-	disable-over-current;
-	status = "okay";
-};
-
-&usdhc1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	bus-width = <4>;
-	no-1-8-v;
-	cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
-	fsl,wp-controller;
-	status = "okay";
-};
-
-&usdhc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	bus-width = <4>;
-	no-1-8-v;
-	cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
-	fsl,wp-controller;
-	status = "okay";
-};