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| author | Linus Walleij <linus.walleij@linaro.org> | 2023-10-20 15:11:41 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2024-01-11 16:21:02 +0100 |
| commit | 18a1ee9d716d355361da2765f87dbbadcdea03bf (patch) | |
| tree | 3dd1bdb61410f516bac606e4fad1ff577456decc /arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_qspi.dts | |
| parent | 3f2f25b5aebffcc73a1afd3bad72c01b6849790a (diff) | |
| download | linux-stable-18a1ee9d716d355361da2765f87dbbadcdea03bf.tar.gz linux-stable-18a1ee9d716d355361da2765f87dbbadcdea03bf.tar.bz2 linux-stable-18a1ee9d716d355361da2765f87dbbadcdea03bf.zip | |
ARM: dts: usr8200: Fix phy registers
The MV88E6060 switch has internal PHY registers at MDIO
addresses 0x00..0x04. Tie each port to the corresponding
PHY.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231020-ixp4xx-usr8200-dtsfix-v1-1-3a8591dea259@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_qspi.dts')
0 files changed, 0 insertions, 0 deletions