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| author | Michael Walle <michael@walle.cc> | 2022-05-03 00:41:18 +0200 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-05-13 16:41:26 +0300 |
| commit | 1e17387a30554c3631faad46a95ab85bfc19d2cc (patch) | |
| tree | 8b2b4af6abb1f82259ad5d9bb8d1d5ede4f91839 /arch/arm/boot/dts/lan966x.dtsi | |
| parent | 99a5f1cbd4bd2c309b3baf1cd7351424171f8905 (diff) | |
| download | linux-stable-1e17387a30554c3631faad46a95ab85bfc19d2cc.tar.gz linux-stable-1e17387a30554c3631faad46a95ab85bfc19d2cc.tar.bz2 linux-stable-1e17387a30554c3631faad46a95ab85bfc19d2cc.zip | |
ARM: dts: lan966x: add all flexcom usart nodes
Add all the remaining usart nodes for the flexcom block. Although the
DMA channels are specified, DMA is not enabled by default because break
detection doesn't work with DMA.
Keep the nodes disabled by default.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220502224127.2604333-5-michael@walle.cc
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Diffstat (limited to 'arch/arm/boot/dts/lan966x.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/lan966x.dtsi | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 230de3bdd5f1..d7eacb0144f5 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -92,6 +92,19 @@ #size-cells = <1>; ranges = <0x0 0xe0040000 0x800>; status = "disabled"; + + usart0: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx1: flexcom@e0044000 { @@ -102,6 +115,19 @@ #size-cells = <1>; ranges = <0x0 0xe0044000 0x800>; status = "disabled"; + + usart1: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; trng: rng@e0048000 { @@ -129,6 +155,19 @@ #size-cells = <1>; ranges = <0x0 0xe0060000 0x800>; status = "disabled"; + + usart2: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx3: flexcom@e0064000 { @@ -181,6 +220,19 @@ #size-cells = <1>; ranges = <0x0 0xe0070000 0x800>; status = "disabled"; + + usart4: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; timer0: timer@e008c000 { |