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| author | Michael Walle <mwalle@kernel.org> | 2024-06-17 11:13:30 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2024-06-27 15:24:41 +0800 |
| commit | edfea889a049abe80f0d55c0365bf60fbade272f (patch) | |
| tree | b48571c77d5941ec2665867a555cfb94d48c74cd /arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | |
| parent | 0df3c7d7a73d75153090637392c0b73a63cdc24a (diff) | |
| download | linux-stable-edfea889a049abe80f0d55c0365bf60fbade272f.tar.gz linux-stable-edfea889a049abe80f0d55c0365bf60fbade272f.tar.bz2 linux-stable-edfea889a049abe80f0d55c0365bf60fbade272f.zip | |
ARM: dts: imx6qdl-kontron-samx6i: fix PHY reset
The PHY reset line is connected to both the SoC (GPIO1_25) and
the CPLD. We must not use the GPIO1_25 as it will drive against
the output buffer of the CPLD. Instead there is another GPIO
(GPIO2_01), an input to the CPLD, which will tell the CPLD to
assert the PHY reset line.
Fixes: 2a51f9dae13d ("ARM: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module")
Fixes: 5694eed98cca ("ARM: dts: imx6qdl-kontron-samx6i: move phy reset into phy-node")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi index d8c1dfb8c9ab..d6c049b9a9c6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -269,7 +269,7 @@ ethphy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; }; }; @@ -516,7 +516,7 @@ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 /* RST_GBE0_PHY# */ >; }; |