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| author | Clément Léger <clement.leger@bootlin.com> | 2022-06-24 16:39:57 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-29 15:28:27 +0200 |
| commit | dc0f67311416c86ed3c6f14a365c8e833ed4b8dd (patch) | |
| tree | 9b3eef292d27333d04e537fff233eaf4aa5611af /arch/arm/boot/dts/r9a06g032.dtsi | |
| parent | d1273f541ab409242e08da6bb836bb564021274c (diff) | |
| download | linux-stable-dc0f67311416c86ed3c6f14a365c8e833ed4b8dd.tar.gz linux-stable-dc0f67311416c86ed3c6f14a365c8e833ed4b8dd.tar.bz2 linux-stable-dc0f67311416c86ed3c6f14a365c8e833ed4b8dd.zip | |
ARM: dts: r9a06g032: Describe MII converter
Add the MII converter node which describes the MII converter that is
present on the RZ/N1 SoC.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Link: https://lore.kernel.org/r/20220624144001.95518-13-clement.leger@bootlin.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm/boot/dts/r9a06g032.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r9a06g032.dtsi | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index d3665910958b..f6241af33112 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -304,6 +304,45 @@ data-width = <8>; }; + eth_miic: eth-miic@44030000 { + compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x44030000 0x10000>; + clocks = <&sysctrl R9A06G032_CLK_MII_REF>, + <&sysctrl R9A06G032_CLK_RGMII_REF>, + <&sysctrl R9A06G032_CLK_RMII_REF>, + <&sysctrl R9A06G032_HCLK_SWITCH_RG>; + clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; + power-domains = <&sysctrl>; + status = "disabled"; + + mii_conv1: mii-conv@1 { + reg = <1>; + status = "disabled"; + }; + + mii_conv2: mii-conv@2 { + reg = <2>; + status = "disabled"; + }; + + mii_conv3: mii-conv@3 { + reg = <3>; + status = "disabled"; + }; + + mii_conv4: mii-conv@4 { + reg = <4>; + status = "disabled"; + }; + + mii_conv5: mii-conv@5 { + reg = <5>; + status = "disabled"; + }; + }; + gic: interrupt-controller@44101000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; interrupt-controller; |