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authorBoris Brezillon <boris.brezillon@free-electrons.com>2014-07-07 18:32:24 +0200
committerNicolas Ferre <nicolas.ferre@atmel.com>2015-03-23 15:37:35 +0100
commite55668914dc6056146189c54975ddac01c0e0dbd (patch)
tree21e3526c2a6f6b05ce60d38e80fcbb4ae6c903b6 /arch/arm/boot/dts/sama5d3_lcd.dtsi
parentee839fdd9ff14fc94e8092aa6f35572b6f760e09 (diff)
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ARM: at91/dt: define the HLCDC node available on sama5d3 SoCs
Define the HLCDC (HLCD Controller) IP available on some sama5d3 SoCs (i.e. sama5d31, sama5d33, sama5d34 and sama5d36) in sama5d3 dtsi file. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Anthony Harivel <anthony.harivel@emtrion.de> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/boot/dts/sama5d3_lcd.dtsi')
-rw-r--r--arch/arm/boot/dts/sama5d3_lcd.dtsi28
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi
index 49038859d84f..be7cfefc6c31 100644
--- a/arch/arm/boot/dts/sama5d3_lcd.dtsi
+++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi
@@ -13,6 +13,34 @@
/ {
ahb {
apb {
+ hlcdc: hlcdc@f0030000 {
+ compatible = "atmel,sama5d3-hlcdc";
+ reg = <0xf0030000 0x2000>;
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+ clock-names = "periph_clk","sys_clk", "slow_clk";
+ status = "disabled";
+
+ hlcdc-display-controller {
+ compatible = "atmel,hlcdc-display-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ };
+
+ hlcdc_pwm: hlcdc-pwm {
+ compatible = "atmel,hlcdc-pwm";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_pwm>;
+ #pwm-cells = <3>;
+ };
+ };
+
pinctrl@fffff200 {
lcd {
pinctrl_lcd_base: lcd-base-0 {