diff options
| author | Alain Volmat <avolmat@me.com> | 2021-03-31 22:42:24 +0200 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@foss.st.com> | 2021-08-06 09:30:02 +0200 |
| commit | a1b68d6b02b6b3d92dc9093d3f56688bc463bb73 (patch) | |
| tree | d847344f13a6c49b3cba2b9c5c9d53c0d53a8dbf /arch/arm/boot/dts/stih418-clock.dtsi | |
| parent | 7f9ed95ddaa5ac0b8894b0fe6bb130c06cafb44d (diff) | |
| download | linux-stable-a1b68d6b02b6b3d92dc9093d3f56688bc463bb73.tar.gz linux-stable-a1b68d6b02b6b3d92dc9093d3f56688bc463bb73.tar.bz2 linux-stable-a1b68d6b02b6b3d92dc9093d3f56688bc463bb73.zip | |
ARM: dts: sti: update clkgen-fsyn entries in stih418-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Diffstat (limited to 'arch/arm/boot/dts/stih418-clock.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/stih418-clock.dtsi | 26 |
1 files changed, 3 insertions, 23 deletions
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index d628e656458d..e84c476b83ed 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -94,11 +94,6 @@ reg = <0x9103000 0x1000>; clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-fs0-ch0", - "clk-s-c0-fs0-ch1", - "clk-s-c0-fs0-ch2", - "clk-s-c0-fs0-ch3"; }; clk_s_c0: clockgen-c@9103000 { @@ -150,15 +145,10 @@ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { #clock-cells = <1>; - compatible = "st,quadfs"; + compatible = "st,quadfs-d0"; reg = <0x9104000 0x1000>; clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d0-fs0-ch0", - "clk-s-d0-fs0-ch1", - "clk-s-d0-fs0-ch2", - "clk-s-d0-fs0-ch3"; }; clockgen-d0@9104000 { @@ -179,15 +169,10 @@ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { #clock-cells = <1>; - compatible = "st,quadfs"; + compatible = "st,quadfs-d2"; reg = <0x9106000 0x1000>; clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d2-fs0-ch0", - "clk-s-d2-fs0-ch1", - "clk-s-d2-fs0-ch2", - "clk-s-d2-fs0-ch3"; }; clockgen-d2@9106000 { @@ -210,15 +195,10 @@ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { #clock-cells = <1>; - compatible = "st,quadfs"; + compatible = "st,quadfs-d3"; reg = <0x9107000 0x1000>; clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d3-fs0-ch0", - "clk-s-d3-fs0-ch1", - "clk-s-d3-fs0-ch2", - "clk-s-d3-fs0-ch3"; }; clockgen-d3@9107000 { |