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| author | Chen-Yu Tsai <wens@csie.org> | 2015-12-01 13:47:20 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2015-12-01 14:08:23 +0100 |
| commit | 1ac56a6da9e11fe35470f804376a67b5bb9d13fe (patch) | |
| tree | caa0d017ad53ff1f37238014071d985daa5596db /arch/arm/boot/dts/sun9i-a80.dtsi | |
| parent | d255abd60e9c0c91e0146fdcbe534b3b9f5352a6 (diff) | |
| download | linux-stable-1ac56a6da9e11fe35470f804376a67b5bb9d13fe.tar.gz linux-stable-1ac56a6da9e11fe35470f804376a67b5bb9d13fe.tar.bz2 linux-stable-1ac56a6da9e11fe35470f804376a67b5bb9d13fe.zip | |
ARM: dts: sun9i: Add A80 R_PIO pin controller device node
The A80 has a secondary pin controller. Add a device node for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun9i-a80.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun9i-a80.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index eb69a62f6bc4..d02ee5d520e2 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -868,5 +868,19 @@ resets = <&apbs_rst 4>; status = "disabled"; }; + + r_pio: pinctrl@08002c00 { + compatible = "allwinner,sun9i-a80-r-pinctrl"; + reg = <0x08002c00 0x400>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&apbs_gates 0>; + resets = <&apbs_rst 0>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; + }; }; }; |