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authorChen-Yu Tsai <wens@csie.org>2014-10-31 11:05:47 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-10-31 09:25:11 +0100
commit6657a05872c2fe0e891edb2be039ad5c231ae985 (patch)
tree3787111adef48bd88fb714fd79cfdefdaf204916 /arch/arm/boot/dts/sun9i-a80.dtsi
parente4aa753a72c16dbdee88383413b4856cd7dba518 (diff)
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ARM: dts: sun9i: Add i2c3 pinmux setting for A80 SoC
i2c3 has only one possible pinmux setting on the A80 SoC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun9i-a80.dtsi')
-rw-r--r--arch/arm/boot/dts/sun9i-a80.dtsi7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 3ec727d76d1b..0a1f1a888308 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -352,6 +352,13 @@
#size-cells = <0>;
#gpio-cells = <3>;
+ i2c3_pins_a: i2c3@0 {
+ allwinner,pins = "PG10", "PG11";
+ allwinner,function = "i2c3";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
uart0_pins_a: uart0@0 {
allwinner,pins = "PH12", "PH13";
allwinner,function = "uart0";