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| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-04-23 17:09:43 +0200 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2023-05-08 11:24:39 -0700 |
| commit | 0db4bb045b038ee8c832d4f19013fd88e8d7fd05 (patch) | |
| tree | 57a26e4a7597255c64f68860f2414c799a312589 /arch/arm/boot | |
| parent | ac9a78681b921877518763ba0e89202254349d1b (diff) | |
| download | linux-stable-0db4bb045b038ee8c832d4f19013fd88e8d7fd05.tar.gz linux-stable-0db4bb045b038ee8c832d4f19013fd88e8d7fd05.tar.bz2 linux-stable-0db4bb045b038ee8c832d4f19013fd88e8d7fd05.zip | |
ARM: dts: broadcom: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
bcm963148.dtb: l2-cache0: 'cache-unified' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/r/20230423150943.118576-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/bcm47622.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/bcm63148.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/bcm63178.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/bcm6756.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/bcm6846.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/bcm6855.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/bcm6878.dtsi | 1 |
7 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi index cd25ed2757b7..7cd38de118c3 100644 --- a/arch/arm/boot/dts/bcm47622.dtsi +++ b/arch/arm/boot/dts/bcm47622.dtsi @@ -52,6 +52,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi index ba7f265db121..24431de1810e 100644 --- a/arch/arm/boot/dts/bcm63148.dtsi +++ b/arch/arm/boot/dts/bcm63148.dtsi @@ -36,6 +36,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi index d8268a1e889b..3f9aed96babf 100644 --- a/arch/arm/boot/dts/bcm63178.dtsi +++ b/arch/arm/boot/dts/bcm63178.dtsi @@ -44,6 +44,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi index 49ecc1f0c18c..1d8d957d65dd 100644 --- a/arch/arm/boot/dts/bcm6756.dtsi +++ b/arch/arm/boot/dts/bcm6756.dtsi @@ -52,6 +52,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi index fbc7d3a5dc5f..cf92cf8c4693 100644 --- a/arch/arm/boot/dts/bcm6846.dtsi +++ b/arch/arm/boot/dts/bcm6846.dtsi @@ -36,6 +36,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/bcm6855.dtsi index 5e0fe26530f1..52d6bc89f9f8 100644 --- a/arch/arm/boot/dts/bcm6855.dtsi +++ b/arch/arm/boot/dts/bcm6855.dtsi @@ -44,6 +44,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi index 96529d3d4dc2..2c5d706bac7e 100644 --- a/arch/arm/boot/dts/bcm6878.dtsi +++ b/arch/arm/boot/dts/bcm6878.dtsi @@ -36,6 +36,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; |