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| author | Anson Huang <Anson.Huang@nxp.com> | 2018-09-30 11:32:26 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2018-09-30 15:31:40 +0800 |
| commit | c90dec00cc84942614bc41f75dc24a87b6d5763b (patch) | |
| tree | d71ca7638f11ab7bbe50666da755c6bc357774b2 /arch/arm/mach-imx/anatop.c | |
| parent | 8148d2136002da2e2887caf6a07bbd9c033f14f3 (diff) | |
| download | linux-stable-c90dec00cc84942614bc41f75dc24a87b6d5763b.tar.gz linux-stable-c90dec00cc84942614bc41f75dc24a87b6d5763b.tar.bz2 linux-stable-c90dec00cc84942614bc41f75dc24a87b6d5763b.zip | |
ARM: imx: add i.mx6ulz msl support
The i.MX 6ULZ processor is a high-performance, ultra
cost-efficient consumer Linux processor featuring an
advanced implementation of a single Arm® Cortex®-A7 core,
which operates at speeds up to 900 MHz.
This patch adds basic MSL support for i.MX6ULZ, the
i.MX6ULZ has same soc_id as i.MX6ULL, and SRC_SBMR2 bit[6]
is to differentiate i.MX6ULZ from i.MX6ULL, 1'b1 means
i.MX6ULZ and 1'b0 means i.MX6ULL.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/mach-imx/anatop.c')
| -rw-r--r-- | arch/arm/mach-imx/anatop.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index 61f3d94f1633..45d618abf26b 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -31,6 +31,8 @@ #define ANADIG_DIGPROG_IMX6SL 0x280 #define ANADIG_DIGPROG_IMX7D 0x800 +#define SRC_SBMR2 0x1c + #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000 #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8 #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 @@ -148,6 +150,24 @@ void __init imx_init_revision_from_anatop(void) major_part = (digprog >> 8) & 0xf; minor_part = digprog & 0xf; revision = ((major_part + 1) << 4) | minor_part; + + if ((digprog >> 16) == MXC_CPU_IMX6ULL) { + void __iomem *src_base; + u32 sbmr2; + + np = of_find_compatible_node(NULL, NULL, + "fsl,imx6ul-src"); + src_base = of_iomap(np, 0); + WARN_ON(!src_base); + sbmr2 = readl_relaxed(src_base + SRC_SBMR2); + iounmap(src_base); + + /* src_sbmr2 bit 6 is to identify if it is i.MX6ULZ */ + if (sbmr2 & (1 << 6)) { + digprog &= ~(0xff << 16); + digprog |= (MXC_CPU_IMX6ULZ << 16); + } + } } mxc_set_cpu_type(digprog >> 16 & 0xff); |