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| author | Arnd Bergmann <arnd@arndb.de> | 2019-09-02 18:37:30 +0200 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2020-08-22 13:02:02 +0200 |
| commit | c6ff132d4224022ffaa461ec771ec27c5319369c (patch) | |
| tree | ce00829c11c36a6ea725ad86f1c023ff9bbf4a40 /arch/arm/mach-s3c/regs-clock-s3c64xx.h | |
| parent | 71b9114d2c13a648fbe6523dd859e611c316ad90 (diff) | |
| download | linux-stable-c6ff132d4224022ffaa461ec771ec27c5319369c.tar.gz linux-stable-c6ff132d4224022ffaa461ec771ec27c5319369c.tar.bz2 linux-stable-c6ff132d4224022ffaa461ec771ec27c5319369c.zip | |
ARM: s3c: make headers local if possible
A lot of header files are only used internally now, so they can be moved
to mach-s3c, out of the visibility of drivers.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20200806182059.2431-40-krzk@kernel.org
[krzk: Rebase and fixup leds-s3c24xx driver]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm/mach-s3c/regs-clock-s3c64xx.h')
| -rw-r--r-- | arch/arm/mach-s3c/regs-clock-s3c64xx.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c/regs-clock-s3c64xx.h b/arch/arm/mach-s3c/regs-clock-s3c64xx.h new file mode 100644 index 000000000000..35a68767b318 --- /dev/null +++ b/arch/arm/mach-s3c/regs-clock-s3c64xx.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX clock register definitions + */ + +#ifndef __PLAT_REGS_CLOCK_H +#define __PLAT_REGS_CLOCK_H __FILE__ + +/* + * FIXME: Remove remaining definitions + */ + +#define S3C_CLKREG(x) (S3C_VA_SYS + (x)) + +#define S3C_PCLK_GATE S3C_CLKREG(0x34) +#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) +#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120) + +/* PCLK GATE Registers */ +#define S3C_CLKCON_PCLK_UART3 (1<<4) +#define S3C_CLKCON_PCLK_UART2 (1<<3) +#define S3C_CLKCON_PCLK_UART1 (1<<2) +#define S3C_CLKCON_PCLK_UART0 (1<<1) + +/* MEM_SYS_CFG */ +#define MEM_SYS_CFG_INDEP_CF 0x4000 +#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 + +#endif /* _PLAT_REGS_CLOCK_H */ |