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author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2013-08-01 23:39:44 -0700 |
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committer | Simon Horman <horms+renesas@verge.net.au> | 2013-08-06 18:07:13 +0900 |
commit | 70e3f3d4f40fe5ecdb351acf33db06df077fb0c1 (patch) | |
tree | f96bdc841b46cf5a2321921c4231e1f079e1bbb5 /arch/arm/mach-shmobile/setup-r8a7740.c | |
parent | 8c23c7caeb5750fcf6d7a0258692071b06fdc772 (diff) | |
download | linux-stable-70e3f3d4f40fe5ecdb351acf33db06df077fb0c1.tar.gz linux-stable-70e3f3d4f40fe5ecdb351acf33db06df077fb0c1.tar.bz2 linux-stable-70e3f3d4f40fe5ecdb351acf33db06df077fb0c1.zip |
ARM: shmobile: r8a7740: move r8a7740_init_irq_of() to setup
This patch moves r8a7740_init_irq_of() to setup code,
and remove intc-r8a7740
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/mach-shmobile/setup-r8a7740.c')
-rw-r--r-- | arch/arm/mach-shmobile/setup-r8a7740.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 21026b349b96..b7d4b2c3bc29 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -22,6 +22,8 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/irqchip.h> +#include <linux/irqchip/arm-gic.h> #include <linux/platform_data/irq-renesas-intc-irqpin.h> #include <linux/platform_device.h> #include <linux/of_platform.h> @@ -1019,6 +1021,36 @@ void __init r8a7740_init_delay(void) shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ }; +void __init r8a7740_init_irq_of(void) +{ + void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); + void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); + void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); + + irqchip_init(); + + /* route signals to GIC */ + iowrite32(0x0, pfc_inta_ctrl); + + /* + * To mask the shared interrupt to SPI 149 we must ensure to set + * PRIO *and* MASK. Else we run into IRQ floods when registering + * the intc_irqpin devices + */ + iowrite32(0x0, intc_prio_base + 0x0); + iowrite32(0x0, intc_prio_base + 0x4); + iowrite32(0x0, intc_prio_base + 0x8); + iowrite32(0x0, intc_prio_base + 0xc); + iowrite8(0xff, intc_msk_base + 0x0); + iowrite8(0xff, intc_msk_base + 0x4); + iowrite8(0xff, intc_msk_base + 0x8); + iowrite8(0xff, intc_msk_base + 0xc); + + iounmap(intc_prio_base); + iounmap(intc_msk_base); + iounmap(pfc_inta_ctrl); +} + static void __init r8a7740_generic_init(void) { r8a7740_clock_init(0); |