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author | James Morris <jmorris@namei.org> | 2011-04-19 21:32:41 +1000 |
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committer | James Morris <jmorris@namei.org> | 2011-04-19 21:32:41 +1000 |
commit | d4ab4e6a23f805abb8fc3cc34525eec3788aeca1 (patch) | |
tree | eefd82c155bc27469a85667d759cd90facf4a6e3 /arch/arm/mm/cache-v7.S | |
parent | c0fa797ae6cd02ff87c0bfe0d509368a3b45640e (diff) | |
parent | 96fd2d57b8252e16dfacf8941f7a74a6119197f5 (diff) | |
download | linux-stable-d4ab4e6a23f805abb8fc3cc34525eec3788aeca1.tar.gz linux-stable-d4ab4e6a23f805abb8fc3cc34525eec3788aeca1.tar.bz2 linux-stable-d4ab4e6a23f805abb8fc3cc34525eec3788aeca1.zip |
Merge branch 'master'; commit 'v2.6.39-rc3' into next
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
-rw-r--r-- | arch/arm/mm/cache-v7.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 6136e68ce953..dc18d81ef8ce 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -96,7 +96,7 @@ ENDPROC(v7_flush_dcache_all) * Flush the entire cache system. * The data cache flush is now achieved using atomic clean / invalidates * working outwards from L1 cache. This is done using Set/Way based cache - * maintainance instructions. + * maintenance instructions. * The instruction cache can still be invalidated back to the point of * unification in a single instruction. * |