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author | Lubomir Rintel <lkundrak@v3.sk> | 2018-11-28 18:53:10 +0100 |
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committer | Olof Johansson <olof@lixom.net> | 2018-11-30 15:13:04 -0800 |
commit | 1147e05ac9fc2ef86a3691e7ca5c2db7602d81dd (patch) | |
tree | 9fc3e30bc9916c2cd3eec5fcb77698226e42a04d /arch/arm/mm/highmem.c | |
parent | 03f64e17f57c0a8041c8fed35de9c0176a730aa5 (diff) | |
download | linux-stable-1147e05ac9fc2ef86a3691e7ca5c2db7602d81dd.tar.gz linux-stable-1147e05ac9fc2ef86a3691e7ca5c2db7602d81dd.tar.bz2 linux-stable-1147e05ac9fc2ef86a3691e7ca5c2db7602d81dd.zip |
ARM: dts: mmp2: fix TWSI2
Marvell keeps their MMP2 datasheet secret, but there are good clues
that TWSI2 is not on 0xd4025000 on that platform, not does it use
IRQ 58. In fact, the IRQ 58 on MMP2 seems to be a signal processor:
arch/arm/mach-mmp/irqs.h:#define IRQ_MMP2_MSP 58
I'm taking a somewhat educated guess that is probably a copy & paste
error from PXA168 or PXA910 and that the real controller in fact hides
at address 0xd4031000 and uses an interrupt line multiplexed via IRQ 17.
I'm also copying some properties from TWSI1 that were missing or
incorrect.
Tested on a OLPC XO 1.75 machine, where the RTC is on TWSI2.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Tested-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mm/highmem.c')
0 files changed, 0 insertions, 0 deletions