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author | Will Deacon <will.deacon@arm.com> | 2016-08-22 11:58:36 +0100 |
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committer | Will Deacon <will.deacon@arm.com> | 2016-08-26 11:33:22 +0100 |
commit | 6ffe9923f2350c19b95a2c9ebf1b4f5f275986f2 (patch) | |
tree | ab5298c631fa96353509174ea1fe883bf0a66310 /arch/arm64/Kconfig | |
parent | b2d8b0cb6ca9cb81dd71626642f764ac70d10813 (diff) | |
download | linux-stable-6ffe9923f2350c19b95a2c9ebf1b4f5f275986f2.tar.gz linux-stable-6ffe9923f2350c19b95a2c9ebf1b4f5f275986f2.tar.bz2 linux-stable-6ffe9923f2350c19b95a2c9ebf1b4f5f275986f2.zip |
arm64: errata: Pass --fix-cortex-a53-843419 to ld if workaround enabled
Cortex-A53 erratum 843419 is worked around by the linker, although it is
a configure-time option to GCC as to whether ld is actually asked to
apply the workaround or not.
This patch ensures that we pass --fix-cortex-a53-843419 to the linker
when both CONFIG_ARM64_ERRATUM_843419=y and the linker supports the
option.
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/Kconfig')
-rw-r--r-- | arch/arm64/Kconfig | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 1e49fbc4b075..0579f6e0a5fd 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -418,18 +418,13 @@ config ARM64_ERRATUM_845719 config ARM64_ERRATUM_843419 bool "Cortex-A53: 843419: A load or store might access an incorrect address" - depends on MODULES default y - select ARM64_MODULE_CMODEL_LARGE + select ARM64_MODULE_CMODEL_LARGE if MODULES help - This option builds kernel modules using the large memory model in - order to avoid the use of the ADRP instruction, which can cause - a subsequent memory access to use an incorrect address on Cortex-A53 - parts up to r0p4. - - Note that the kernel itself must be linked with a version of ld - which fixes potentially affected ADRP instructions through the - use of veneers. + This option links the kernel with '--fix-cortex-a53-843419' and + builds modules using the large memory model in order to avoid the use + of the ADRP instruction, which can cause a subsequent memory access + to use an incorrect address on Cortex-A53 parts up to r0p4. If unsure, say Y. |