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author | Gregory CLEMENT <gregory.clement@bootlin.com> | 2018-09-21 18:09:15 +0200 |
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committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2018-10-02 16:46:52 +0200 |
commit | 92e5d4e9398eabf997075bed2543d7fd783e1ab0 (patch) | |
tree | 35cf0fda0175218772db2d37a62e8ce5bbdd7996 /arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi | |
parent | 620cfb31bad4c5be7d9250f1e47a592750fc364b (diff) | |
download | linux-stable-92e5d4e9398eabf997075bed2543d7fd783e1ab0.tar.gz linux-stable-92e5d4e9398eabf997075bed2543d7fd783e1ab0.tar.bz2 linux-stable-92e5d4e9398eabf997075bed2543d7fd783e1ab0.zip |
arm64: dts: marvell: Add node labels for the cpus
Aligned with what we have done for the others nodes. It will also allow
to easily modify the cpu configuration at board (or sub-SoC) level.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi index 7d00ae78fc79..b788cb63caf2 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi @@ -13,49 +13,49 @@ #size-cells = <0>; compatible = "marvell,armada-ap810-octa"; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x000>; enable-method = "psci"; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x001>; enable-method = "psci"; }; - cpu@100 { + cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x100>; enable-method = "psci"; }; - cpu@101 { + cpu3: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x101>; enable-method = "psci"; }; - cpu@200 { + cpu4: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x200>; enable-method = "psci"; }; - cpu@201 { + cpu5: cpu@201 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x201>; enable-method = "psci"; }; - cpu@300 { + cpu6: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x300>; enable-method = "psci"; }; - cpu@301 { + cpu7: cpu@301 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x301>; |