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| author | Gregory CLEMENT <gregory.clement@bootlin.com> | 2018-02-13 17:32:10 +0100 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2018-02-14 11:40:37 +0100 |
| commit | a7cbf0b2d9c2f7d549da0834599fdba28245d6dd (patch) | |
| tree | 6862f4fdd33c7dc25fce8eb2daca6dcb53b9bf3b /arch/arm64/boot/dts/marvell | |
| parent | 7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff) | |
| download | linux-stable-a7cbf0b2d9c2f7d549da0834599fdba28245d6dd.tar.gz linux-stable-a7cbf0b2d9c2f7d549da0834599fdba28245d6dd.tar.bz2 linux-stable-a7cbf0b2d9c2f7d549da0834599fdba28245d6dd.zip | |
ARM64: dts: marvell: armada-cp110: Add registers clock for SPI nodes
This extra clock is needed to access the registers of the SPI controller
used on Armada 7K/8K SoCs.
This follows the changes already made in the binding documentation (as
well as in the driver) in:
'commit 92ae112e477ac412decc3fdd5c1eeb6c90c266b4 ("spi: orion: Fix clock
resource by adding an optional bus clock")'.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index a8af4136dbe7..0ab921861a2f 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -257,7 +257,9 @@ reg = <0x700600 0x50>; #address-cells = <0x1>; #size-cells = <0x0>; - clocks = <&CP110_LABEL(clk) 1 21>; + clock-names = "core", "axi"; + clocks = <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; status = "disabled"; }; @@ -266,7 +268,9 @@ reg = <0x700680 0x50>; #address-cells = <1>; #size-cells = <0>; - clocks = <&CP110_LABEL(clk) 1 21>; + clock-names = "core", "axi"; + clocks = <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; status = "disabled"; }; |