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author | Pierre Gondois <pierre.gondois@arm.com> | 2022-11-07 16:57:08 +0100 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2022-11-21 13:30:14 +0100 |
commit | 27f1568b1d5fe35014074f92717b250afbe67031 (patch) | |
tree | 43d32cc36641515a91d52856f368c575a4514600 /arch/arm64/boot/dts/nvidia | |
parent | 14910d68718cae5f287c95997dcc9a99531109d6 (diff) | |
download | linux-stable-27f1568b1d5fe35014074f92717b250afbe67031.tar.gz linux-stable-27f1568b1d5fe35014074f92717b250afbe67031.tar.bz2 linux-stable-27f1568b1d5fe35014074f92717b250afbe67031.zip |
arm64: tegra: Update cache properties
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia')
-rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 | ||||
-rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 | ||||
-rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra234.dtsi | 33 |
3 files changed, 49 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index a6721bb82bbd..e64b4a048efd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -3050,36 +3050,51 @@ }; l2c_0: l2-cache0 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l2c_1: l2-cache1 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l2c_2: l2-cache2 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l2c_3: l2-cache3 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l3c: l3-cache { + compatible = "cache"; + cache-unified; cache-size = <4194304>; cache-line-size = <64>; + cache-level = <3>; cache-sets = <4096>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 0cdad97b6962..046ce8ebd505 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -2004,6 +2004,7 @@ L2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 97d47327afdd..8baeed783903 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -3084,117 +3084,150 @@ }; l2c0_0: l2-cache00 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c0_1: l2-cache01 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c0_2: l2-cache02 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c0_3: l2-cache03 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c1_0: l2-cache10 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c1_1: l2-cache11 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c1_2: l2-cache12 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c1_3: l2-cache13 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c2_0: l2-cache20 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l2c2_1: l2-cache21 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l2c2_2: l2-cache22 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l2c2_3: l2-cache23 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l3c0: l3-cache0 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <3>; }; l3c1: l3-cache1 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <3>; }; l3c2: l3-cache2 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <3>; }; }; |