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| author | Olof Johansson <olof@lixom.net> | 2019-06-25 04:31:37 -0700 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2019-06-25 04:31:37 -0700 |
| commit | 750ee7858f5ae2894c0b12171fad3c8170c1e26c (patch) | |
| tree | 8cb41634afe1193d63f324042ef34640eb73571f /arch/arm64/boot/dts/qcom/msm8916.dtsi | |
| parent | 0914acd87fa089983f184785491d939a53f73e94 (diff) | |
| parent | 2410fd450c09a126aefefc9106b4652285b5d60f (diff) | |
| download | linux-stable-750ee7858f5ae2894c0b12171fad3c8170c1e26c.tar.gz linux-stable-750ee7858f5ae2894c0b12171fad3c8170c1e26c.tar.bz2 linux-stable-750ee7858f5ae2894c0b12171fad3c8170c1e26c.zip | |
Merge tag 'qcom-arm64-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
Qualcomm ARM64 Updates for v5.3
* Switch to use second gen PON on PM8998
* Add PSCI cupidle states for MSM8996, MSM8998,and SDM845
* Add MSM8996 UFS phy reset controller
* Add propre cpu capacity scaling on MSM8996
* Fixups for APR domain, legacy clocks, and PSCI entry latency on MSM8996
* Enable SMMUs on MSM8996
* Add Dragonboard 845C
* Add Q6V5, GPU, GMU, and AOSS QMP node on SDM845
* Fixup CPU topology on SDM845
* Change USB1 to be peripheral on SDM845 MTP
* Add PCIe Phy, RC nodes, ANOC1 SMMU, and RPMPD node on MSM8998
* Update coresight bindings for MSM8916
* Update idle state names and entry-method on MSM8916
* Add PCIe, RPMPD, LPASS, Q6, TCSR, TuringCC, PSCI cpuidle states,
and CDSP on QCS404
* Add reset-cells property to QCS404 GCC node
* Fixup s3 max voltage, l3 min voltage, drive strength typo, and
s3 supply definition on QCS404-evb
* Fixup ADC outputs and VADC calibration on PMS405
* tag 'qcom-arm64-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (39 commits)
arm64: dts: qcom: qcs404-evb: fix vdd_apc supply
arm64: dts: qcom: pm8998: Use qcom,pm8998-pon binding for second gen pon
arm64: dts: qcom: msm8996: Enable SMMUs
arm64: dts: qcom: msm8996: Correct apr-domain property
arm64: dts: qcom: Add Dragonboard 845c
arm64: dts: qcom: qcs404-evb: Enable PCIe
arm64: dts: qcom: qcs404: Add PCIe related nodes
arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes
arm64: dts: qcom: msm8998: Add ANOC1 SMMU node
arm64: dts: qcom: msm8996: Stop using legacy clock names
arm64: dts: msm8996: fix PSCI entry-latency-us
arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states
arm64: dts: qcom: sdm845: Add Q6V5 MSS node
arm64: dts: qcom: Add AOSS QMP node
arm64: dts: qcom-qcs404: Add reset-cells to GCC node
arm64: dts: qcom-msm8916: Update coresight DT bindings
arm64: dts: qcom: msm8998: Add rpmpd node
arm64: dts: qcom: qcs404: Add rpmpd node
arm64: dts: qcom: qcs404: Move lpass and q6 into soc
arm64: dts: qcom: qcs404: Fully describe the CDSP
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/msm8916.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8916.dtsi | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index dacd465fc62e..5ea9fb8f2f87 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -102,7 +102,7 @@ reg = <0x0>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -114,7 +114,7 @@ reg = <0x1>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -126,7 +126,7 @@ reg = <0x2>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -138,7 +138,7 @@ reg = <0x3>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -150,8 +150,11 @@ }; idle-states { - CPU_SPC: spc { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; + idle-state-name = "standalone-power-collapse"; arm,psci-suspend-param = <0x40000002>; entry-latency-us = <130>; exit-latency-us = <150>; @@ -1164,7 +1167,7 @@ }; funnel@821000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x821000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; @@ -1277,7 +1280,7 @@ }; funnel@841000 { /* APSS funnel only 4 inputs are used */ - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x841000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; |