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authorMichael Srba <michael.srba@seznam.cz>2022-04-11 09:21:56 +0200
committerBjorn Andersson <bjorn.andersson@linaro.org>2022-04-19 12:07:24 -0500
commit1ed29355df221407370933522a94dc8a0f47eb35 (patch)
tree8e9b207366ad052a7de679a0bac4b39bc2aa2afd /arch/arm64/boot/dts/qcom/msm8998.dtsi
parent0fb9ddbc6311202a9b904f5f2c0c7961f9a98d98 (diff)
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arm64: dts: qcom: msm8998: reserve potentially inaccessible clocks
With the gcc driver now being more complete and describing clocks which might not always be write-accessible to the OS, conservatively specify all such clocks as protected in the SoC dts. The board dts - or even user-supplied dts - can override this property to reflect the actual configuration. Signed-off-by: Michael Srba <michael.srba@seznam.cz> Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220411072156.24451-6-michael.srba@seznam.cz
Diffstat (limited to 'arch/arm64/boot/dts/qcom/msm8998.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/msm8998.dtsi15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 2fda21e810c9..4a84de6cee1e 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -815,6 +815,21 @@
clock-names = "xo", "sleep_clk";
clocks = <&xo>, <&sleep_clk>;
+
+ /*
+ * The hypervisor typically configures the memory region where these clocks
+ * reside as read-only for the HLOS. If the HLOS tried to enable or disable
+ * these clocks on a device with such configuration (e.g. because they are
+ * enabled but unused during boot-up), the device will most likely decide
+ * to reboot.
+ * In light of that, we are conservative here and we list all such clocks
+ * as protected. The board dts (or a user-supplied dts) can override the
+ * list of protected clocks if it differs from the norm, and it is in fact
+ * desired for the HLOS to manage these clocks
+ */
+ protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
+ <SSC_XO>,
+ <SSC_CNOC_AHBS_CLK>;
};
rpm_msg_ram: sram@778000 {