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authorAlim Akhtar <alim.akhtar@samsung.com>2022-05-18 18:53:50 +0530
committerKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>2022-06-06 10:31:37 +0200
commit5355559555b98cd2f0b96b2c4e56c32356f90cc1 (patch)
tree5f1e9a35c8c777e04064cb13e66be5089ecb80e0 /arch/arm64/boot/dts/tesla
parentf2906aa863381afb0015a9eb7fefad885d4e5a56 (diff)
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arm64: dts: fsd: Add cpu cache information
Add CPU caches information so that the same is available to userspace via sysfs. This SoC has 48/32 KB I/D cache for each CPU cores and 4MB of L2 cache. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220518132350.35762-1-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts/tesla')
-rw-r--r--arch/arm64/boot/dts/tesla/fsd.dtsi91
1 files changed, 91 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index af39655331de..49a6f0201021 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -93,6 +93,13 @@
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl0_1: cpu@1 {
@@ -102,6 +109,13 @@
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl0_2: cpu@2 {
@@ -111,6 +125,13 @@
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl0_3: cpu@3 {
@@ -119,6 +140,13 @@
reg = <0x0 0x003>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
/* Cluster 1 */
@@ -129,6 +157,13 @@
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl1_1: cpu@101 {
@@ -138,6 +173,13 @@
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl1_2: cpu@102 {
@@ -147,6 +189,13 @@
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl1_3: cpu@103 {
@@ -156,6 +205,13 @@
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
/* Cluster 2 */
@@ -166,6 +222,13 @@
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl2_1: cpu@201 {
@@ -175,6 +238,13 @@
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl2_2: cpu@202 {
@@ -184,6 +254,13 @@
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl2_3: cpu@203 {
@@ -193,6 +270,20 @@
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
+ };
+
+ cpucl_l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x400000>;
+ cache-line-size = <64>;
+ cache-sets = <4096>;
};
idle-states {