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author | Chris Zhong <zyw@rock-chips.com> | 2018-02-13 15:35:48 +0100 |
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committer | Heiko Stuebner <heiko@sntech.de> | 2018-02-14 10:25:40 +0100 |
commit | 2d3c2d56a3355d86a10fc74c82cc8753fb7f9eb5 (patch) | |
tree | 945a792c42659e9508e08c1491b65c5e657e4b95 /arch/arm64/boot | |
parent | 0efaf807839375b3a20366b8a057694c0ccad37b (diff) | |
download | linux-stable-2d3c2d56a3355d86a10fc74c82cc8753fb7f9eb5.tar.gz linux-stable-2d3c2d56a3355d86a10fc74c82cc8753fb7f9eb5.tar.bz2 linux-stable-2d3c2d56a3355d86a10fc74c82cc8753fb7f9eb5.zip |
arm64: dts: rockchip: add cdn-dp node for rk3399.
Add a node for the cdn DP controller which is embedded in the rk3399
SoC.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
[fixed whitespaces instead of tabs, dropped unnecessary address+size-cells
and fixed the number of interrupt cells]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index f689b1363f9c..65a42eee01de 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -457,6 +457,42 @@ }; }; + cdn_dp: dp@fec00000 { + compatible = "rockchip,rk3399-cdn-dp"; + reg = <0x0 0xfec00000 0x0 0x100000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru SCLK_DP_CORE>; + assigned-clock-rates = <100000000>; + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, + <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; + clock-names = "core-clk", "pclk", "spdif", "grf"; + phys = <&tcphy0_dp>, <&tcphy1_dp>; + power-domains = <&power RK3399_PD_HDCP>; + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, + <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; + reset-names = "spdif", "dptx", "apb", "core"; + rockchip,grf = <&grf>; + #sound-dai-cells = <1>; + status = "disabled"; + + ports { + dp_in: port { + #address-cells = <1>; + #size-cells = <0>; + + dp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dp>; + }; + + dp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dp>; + }; + }; + }; + }; + gic: interrupt-controller@fee00000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; @@ -1547,6 +1583,11 @@ reg = <3>; remote-endpoint = <&mipi1_in_vopl>; }; + + vopl_out_dp: endpoint@4 { + reg = <4>; + remote-endpoint = <&dp_in_vopl>; + }; }; }; @@ -1599,6 +1640,11 @@ reg = <3>; remote-endpoint = <&mipi1_in_vopb>; }; + + vopb_out_dp: endpoint@4 { + reg = <4>; + remote-endpoint = <&dp_in_vopb>; + }; }; }; |