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author | James Liao <jamesjj.liao@mediatek.com> | 2015-08-10 17:50:28 +0800 |
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committer | Matthias Brugger <matthias.bgg@gmail.com> | 2015-10-14 15:24:16 +0200 |
commit | 67e56c5651d30cd5adddcf32ab41c71dabf2bcec (patch) | |
tree | fba860066bb06c135eb1aa236b48d74c835c907d /arch/arm64/boot | |
parent | b0c936f59c8928dac2b230322dd51cbfae289151 (diff) | |
download | linux-stable-67e56c5651d30cd5adddcf32ab41c71dabf2bcec.tar.gz linux-stable-67e56c5651d30cd5adddcf32ab41c71dabf2bcec.tar.bz2 linux-stable-67e56c5651d30cd5adddcf32ab41c71dabf2bcec.zip |
arm64: dts: mt8173: Add subsystem clock controller device nodes
This patch adds device nodes providing subsystem clocks on MT8173,
includes mmsys, imgsys, vdecsys, vencsys and vencltsys.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8173.dtsi | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 4bce1676fbd1..42540b208a8f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -116,6 +116,13 @@ clock-output-names = "clk32k"; }; + cpum_ck: oscillator@2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "cpum_ck"; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; @@ -500,6 +507,36 @@ clock-names = "source", "hclk"; status = "disabled"; }; + + mmsys: clock-controller@14000000 { + compatible = "mediatek,mt8173-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: clock-controller@15000000 { + compatible = "mediatek,mt8173-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt8173-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@18000000 { + compatible = "mediatek,mt8173-vencsys", "syscon"; + reg = <0 0x18000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencltsys: clock-controller@19000000 { + compatible = "mediatek,mt8173-vencltsys", "syscon"; + reg = <0 0x19000000 0 0x1000>; + #clock-cells = <1>; + }; }; }; |