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author | Vincenzo Frascino <vincenzo.frascino@arm.com> | 2019-09-16 11:51:17 +0100 |
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committer | Catalin Marinas <catalin.marinas@arm.com> | 2020-09-04 12:46:06 +0100 |
commit | 637ec831ea4f09c7529ac4078399ce4e25b46341 (patch) | |
tree | 7f8a21f46e15ffc6958c46a202ab8d578b23fb9c /arch/arm64/include/asm/mte.h | |
parent | 74f1082487feb90bbf880af14beb8e29c3030c9f (diff) | |
download | linux-stable-637ec831ea4f09c7529ac4078399ce4e25b46341.tar.gz linux-stable-637ec831ea4f09c7529ac4078399ce4e25b46341.tar.bz2 linux-stable-637ec831ea4f09c7529ac4078399ce4e25b46341.zip |
arm64: mte: Handle synchronous and asynchronous tag check faults
The Memory Tagging Extension has two modes of notifying a tag check
fault at EL0, configurable through the SCTLR_EL1.TCF0 field:
1. Synchronous raising of a Data Abort exception with DFSC 17.
2. Asynchronous setting of a cumulative bit in TFSRE0_EL1.
Add the exception handler for the synchronous exception and handling of
the asynchronous TFSRE0_EL1.TF0 bit setting via a new TIF flag in
do_notify_resume().
On a tag check failure in user-space, whether synchronous or
asynchronous, a SIGSEGV will be raised on the faulting thread.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Co-developed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include/asm/mte.h')
-rw-r--r-- | arch/arm64/include/asm/mte.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/mte.h b/arch/arm64/include/asm/mte.h new file mode 100644 index 000000000000..a0bf310da74b --- /dev/null +++ b/arch/arm64/include/asm/mte.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 ARM Ltd. + */ +#ifndef __ASM_MTE_H +#define __ASM_MTE_H + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_ARM64_MTE + +void flush_mte_state(void); + +#else + +static inline void flush_mte_state(void) +{ +} + +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_MTE_H */ |