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authorMarc Zyngier <maz@kernel.org>2024-02-19 15:13:22 +0000
committerCatalin Marinas <catalin.marinas@arm.com>2024-02-19 16:33:12 +0000
commit2aea7b77aabc708a9df769ad5fa63e9912ceb7f7 (patch)
tree659288f5362eb5417479362d9a692b660f8317a7 /arch/arm64/kernel
parent90e636f60b76c590aded72964543945084d97c2f (diff)
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arm64: Use Signed/Unsigned enums for TGRAN{4,16,64} and VARange
Open-coding the feature matching parameters for LVA/LVA2 leads to issues with upcoming changes to the cpufeature code. By making TGRAN{4,16,64} and VARange signed/unsigned as per the architecture, we can use the existing macros, making the feature match robust against those changes. Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/kernel')
-rw-r--r--arch/arm64/kernel/cpufeature.c15
1 files changed, 3 insertions, 12 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 0be9296e9253..d380ae783b73 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2706,24 +2706,15 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.capability = ARM64_HAS_VA52,
.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
.matches = has_cpuid_feature,
- .field_width = 4,
#ifdef CONFIG_ARM64_64K_PAGES
.desc = "52-bit Virtual Addressing (LVA)",
- .sign = FTR_SIGNED,
- .sys_reg = SYS_ID_AA64MMFR2_EL1,
- .field_pos = ID_AA64MMFR2_EL1_VARange_SHIFT,
- .min_field_value = ID_AA64MMFR2_EL1_VARange_52,
+ ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52)
#else
.desc = "52-bit Virtual Addressing (LPA2)",
- .sys_reg = SYS_ID_AA64MMFR0_EL1,
#ifdef CONFIG_ARM64_4K_PAGES
- .sign = FTR_SIGNED,
- .field_pos = ID_AA64MMFR0_EL1_TGRAN4_SHIFT,
- .min_field_value = ID_AA64MMFR0_EL1_TGRAN4_52_BIT,
+ ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT)
#else
- .sign = FTR_UNSIGNED,
- .field_pos = ID_AA64MMFR0_EL1_TGRAN16_SHIFT,
- .min_field_value = ID_AA64MMFR0_EL1_TGRAN16_52_BIT,
+ ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT)
#endif
#endif
},