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| author | Rob Herring <robh@kernel.org> | 2023-09-21 14:41:52 -0500 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2023-09-29 16:31:33 +0100 |
| commit | 471470bc7052d28ce125901877dd10e4c048e513 (patch) | |
| tree | 37c35c9f68345e85f27589662970da97308f69c6 /arch/arm64/tools/cpucaps | |
| parent | a654a69b9f9c06b2e56387d0b99f0e3e6b0ff4ef (diff) | |
| download | linux-stable-471470bc7052d28ce125901877dd10e4c048e513.tar.gz linux-stable-471470bc7052d28ce125901877dd10e4c048e513.tar.bz2 linux-stable-471470bc7052d28ce125901877dd10e4c048e513.zip | |
arm64: errata: Add Cortex-A520 speculative unprivileged load workaround
Implement the workaround for ARM Cortex-A520 erratum 2966298. On an
affected Cortex-A520 core, a speculatively executed unprivileged load
might leak data from a privileged load via a cache side channel. The
issue only exists for loads within a translation regime with the same
translation (e.g. same ASID and VMID). Therefore, the issue only affects
the return to EL0.
The workaround is to execute a TLBI before returning to EL0 after all
loads of privileged data. A non-shareable TLBI to any address is
sufficient.
The workaround isn't necessary if page table isolation (KPTI) is
enabled, but for simplicity it will be. Page table isolation should
normally be disabled for Cortex-A520 as it supports the CSV3 feature
and the E0PD feature (used when KASLR is enabled).
Cc: stable@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230921194156.1050055-2-robh@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/tools/cpucaps')
| -rw-r--r-- | arch/arm64/tools/cpucaps | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index c3f06fdef609..dea3dc89234b 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -84,6 +84,7 @@ WORKAROUND_2077057 WORKAROUND_2457168 WORKAROUND_2645198 WORKAROUND_2658417 +WORKAROUND_2966298 WORKAROUND_AMPERE_AC03_CPU_38 WORKAROUND_TRBE_OVERWRITE_FILL_MODE WORKAROUND_TSB_FLUSH_FAILURE |