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| author | Alex Bee <knaerzche@gmail.com> | 2023-08-29 23:40:05 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2023-10-04 23:27:04 +0200 |
| commit | 02941bc2a1bc8ea82617ba1fd4d2c0643399a9ea (patch) | |
| tree | fb6df424a2ed3639e4bb3170240d7064bb60713e /arch/arm | |
| parent | 9107283badc7d058e34ef3b60a52afe6a5e0acfb (diff) | |
| download | linux-stable-02941bc2a1bc8ea82617ba1fd4d2c0643399a9ea.tar.gz linux-stable-02941bc2a1bc8ea82617ba1fd4d2c0643399a9ea.tar.bz2 linux-stable-02941bc2a1bc8ea82617ba1fd4d2c0643399a9ea.zip | |
ARM: dts: rockchip: Add CPU resets for RK3128
In order to support bring-up of the non-boot cores, this patch adds the
reset controls for the cpu cores.
They are required/will be used by the Rockchip platsmp driver.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829214004.314932-6-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/rockchip/rk3128.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index 3a0856973795..2778049003a1 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -34,6 +34,7 @@ reg = <0xf00>; clock-latency = <40000>; clocks = <&cru ARMCLK>; + resets = <&cru SRST_CORE0>; operating-points = < /* KHz uV */ 816000 1000000 @@ -45,18 +46,21 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf01>; + resets = <&cru SRST_CORE1>; }; cpu2: cpu@f02 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf02>; + resets = <&cru SRST_CORE2>; }; cpu3: cpu@f03 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf03>; + resets = <&cru SRST_CORE3>; }; }; |