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| author | Alex Bee <knaerzche@gmail.com> | 2023-08-29 23:40:09 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2023-10-04 23:27:04 +0200 |
| commit | c96b13d7c0e494e1072648301e61e13a2a85a362 (patch) | |
| tree | a05b67580ce87c3310524bbc3af50361232819f3 /arch/arm | |
| parent | da8b973957ca03f05f78384f2bf6d79a3fce9fb0 (diff) | |
| download | linux-stable-c96b13d7c0e494e1072648301e61e13a2a85a362.tar.gz linux-stable-c96b13d7c0e494e1072648301e61e13a2a85a362.tar.bz2 linux-stable-c96b13d7c0e494e1072648301e61e13a2a85a362.zip | |
ARM: dts: rockchip: Switch to operating-points-v2 for RK3128's CPU
This will allow frequency-scaling for the cpu-cores.
Operating frequencies and voltages have been taken from Rockchip's
downstream kernel.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829214004.314932-10-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/rockchip/rk3128.dtsi | 43 |
1 files changed, 39 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index 877854dd765d..71964262cd5f 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -36,10 +36,7 @@ clock-latency = <40000>; clocks = <&cru ARMCLK>; resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; + operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ }; @@ -48,6 +45,7 @@ compatible = "arm,cortex-a7"; reg = <0xf01>; resets = <&cru SRST_CORE1>; + operating-points-v2 = <&cpu_opp_table>; }; cpu2: cpu@f02 { @@ -55,6 +53,7 @@ compatible = "arm,cortex-a7"; reg = <0xf02>; resets = <&cru SRST_CORE2>; + operating-points-v2 = <&cpu_opp_table>; }; cpu3: cpu@f03 { @@ -62,6 +61,42 @@ compatible = "arm,cortex-a7"; reg = <0xf03>; resets = <&cru SRST_CORE3>; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <950000 950000 1325000>; + }; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1325000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000 950000 1325000>; + }; + opp-696000000 { + opp-hz = /bits/ 64 <696000000>; + opp-microvolt = <975000 975000 1325000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1075000 1075000 1325000>; + opp-suspend; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1200000 1200000 1325000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1325000 1325000 1325000>; }; }; |