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author | Tiezhu Yang <yangtiezhu@loongson.cn> | 2023-06-29 20:58:44 +0800 |
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committer | Huacai Chen <chenhuacai@loongson.cn> | 2023-06-29 20:58:44 +0800 |
commit | 3d2c3daf82544283c5597028a8a3efc9ac0fb02b (patch) | |
tree | 18b7060e3ce945f8b3b378faebd076cb6bbe16f2 /arch/loongarch/kernel/inst.c | |
parent | 7b0a096436c2dac6de77d132e751a8a3328798d5 (diff) | |
download | linux-stable-3d2c3daf82544283c5597028a8a3efc9ac0fb02b.tar.gz linux-stable-3d2c3daf82544283c5597028a8a3efc9ac0fb02b.tar.bz2 linux-stable-3d2c3daf82544283c5597028a8a3efc9ac0fb02b.zip |
LoongArch: Move three functions from kprobes.c to inst.c
The three functions insns_not_supported(), insns_need_simulation() and
arch_simulate_insn() will be used for uprobes, move them from kprobes.c
to inst.c, this is preparation for later patch, no functionality change.
Tested-by: Jeff Xie <xiehuan09@gmail.com>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/kernel/inst.c')
-rw-r--r-- | arch/loongarch/kernel/inst.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/loongarch/kernel/inst.c b/arch/loongarch/kernel/inst.c index ffe13c5ba557..18e197515d7f 100644 --- a/arch/loongarch/kernel/inst.c +++ b/arch/loongarch/kernel/inst.c @@ -133,6 +133,45 @@ void simu_branch(struct pt_regs *regs, union loongarch_instruction insn) } } +bool insns_not_supported(union loongarch_instruction insn) +{ + switch (insn.reg2i14_format.opcode) { + case llw_op: + case lld_op: + case scw_op: + case scd_op: + pr_notice("ll and sc instructions are not supported\n"); + return true; + } + + switch (insn.reg1i21_format.opcode) { + case bceqz_op: + pr_notice("bceqz and bcnez instructions are not supported\n"); + return true; + } + + return false; +} + +bool insns_need_simulation(union loongarch_instruction insn) +{ + if (is_pc_ins(&insn)) + return true; + + if (is_branch_ins(&insn)) + return true; + + return false; +} + +void arch_simulate_insn(union loongarch_instruction insn, struct pt_regs *regs) +{ + if (is_pc_ins(&insn)) + simu_pc(regs, insn); + else if (is_branch_ins(&insn)) + simu_branch(regs, insn); +} + int larch_insn_read(void *addr, u32 *insnp) { int ret; |