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| author | Artur Rojek <contact@artur-rojek.eu> | 2021-08-31 01:01:39 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2021-09-13 02:00:27 +0100 |
| commit | 7b3fd8109b5d343b535e796328223b4f1c4aff5c (patch) | |
| tree | c000b0039d5dac1e1f86e8f23f9e260046237c31 /arch/mips/boot/dts/ingenic/ci20.dts | |
| parent | ae5f94cc00a7fdce830fd4bfe7a8c77ae7704666 (diff) | |
| download | linux-stable-7b3fd8109b5d343b535e796328223b4f1c4aff5c.tar.gz linux-stable-7b3fd8109b5d343b535e796328223b4f1c4aff5c.tar.bz2 linux-stable-7b3fd8109b5d343b535e796328223b4f1c4aff5c.zip | |
MIPS: JZ4780: CI20: DTS: add SPI controller config
1. Add nodes for the two SPI controllers found in MIPS Creator CI20.
2. Reparent SPI clock source to effectively use MPLL and set its clock
rate to 54MHz.
NOTE: To use the SPI controllers, `pinctrl-0` property must be set in
order to configure the used pins. As SPI functionality is multiplexed on
multiple pin groups, this choice is left to the user.
An example configuration:
```
&spi0 {
pinctrl-0 = <&pins_spi0>;
}
pins_spi0: spi0 {
function = "ssi0";
groups = "ssi0-dt-e", "ssi0-dr-e", "ssi0-clk-e",
"ssi0-ce0-e", "ssi0-ce1-e";
bias-disable;
};
```
Consult the CI20 pinout description for more details.
Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
Link: https://lore.kernel.org/r/20210830230139.21476-4-contact@artur-rojek.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'arch/mips/boot/dts/ingenic/ci20.dts')
| -rw-r--r-- | arch/mips/boot/dts/ingenic/ci20.dts | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index a688809beebc..b249a4f0f6b6 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -113,9 +113,12 @@ * Use the 32.768 kHz oscillator as the parent of the RTC for a higher * precision. */ - assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>; - assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>; - assigned-clock-rates = <48000000>; + assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>, + <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>; + assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>, + <&cgu JZ4780_CLK_MPLL>, + <&cgu JZ4780_CLK_SSIPLL>; + assigned-clock-rates = <48000000>, <0>, <54000000>; }; &tcu { |