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author | 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> | 2020-11-17 01:55:07 +0800 |
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committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-11-17 21:37:49 +0100 |
commit | 158c774d3c64859e84dd20e04d5fb18c8d3d318e (patch) | |
tree | fdab27dcef208e99bc323330829e457c1f9dc645 /arch/mips/boot/dts/ingenic/cu1000-neo.dts | |
parent | 7701f264a756d41c2b663c3b745dd81efc875515 (diff) | |
download | linux-stable-158c774d3c64859e84dd20e04d5fb18c8d3d318e.tar.gz linux-stable-158c774d3c64859e84dd20e04d5fb18c8d3d318e.tar.bz2 linux-stable-158c774d3c64859e84dd20e04d5fb18c8d3d318e.zip |
MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.
1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
nodes for CU1000-Neo.
3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
nodes for CU1830-Neo.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Tested by: H. Nikolaus Schaller <hns@goldelico.com> # CI20/jz4780
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/boot/dts/ingenic/cu1000-neo.dts')
-rw-r--r-- | arch/mips/boot/dts/ingenic/cu1000-neo.dts | 62 |
1 files changed, 56 insertions, 6 deletions
diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts b/arch/mips/boot/dts/ingenic/cu1000-neo.dts index 22a1066d637b..f98cf029efc3 100644 --- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts +++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts @@ -3,7 +3,7 @@ #include "x1000.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/clock/ingenic,tcu.h> +#include <dt-bindings/clock/ingenic,sysost.h> #include <dt-bindings/interrupt-controller/irq.h> / { @@ -31,6 +31,42 @@ }; }; + ssi: spi-gpio { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + num-chipselects = <1>; + + mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>; + + status = "okay"; + + spi-max-frequency = <50000000>; + + sc16is752: expander@0 { + compatible = "nxp,sc16is752"; + reg = <0>; /* CE0 */ + spi-max-frequency = <4000000>; + + clocks = <&exclk_sc16is752>; + + interrupt-parent = <&gpc>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + exclk_sc16is752: sc16is752 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + }; + }; + wlan_pwrseq: msc1-pwrseq { compatible = "mmc-pwrseq-simple"; @@ -43,13 +79,19 @@ clock-frequency = <24000000>; }; -&tcu { +&cgu { + /* + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher + * precision. + */ + assigned-clocks = <&cgu X1000_CLK_RTC>; + assigned-clock-parents = <&cgu X1000_CLK_RTCLK>; +}; + +&ost { /* 1500 kHz for the system timer and clocksource */ - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>; + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>; assigned-clock-rates = <1500000>, <1500000>; - - /* Use channel #0 for the system timer channel #2 for the clocksource */ - ingenic,pwm-channels-mask = <0xfa>; }; &uart2 { @@ -135,6 +177,14 @@ }; }; +&otg_phy { + status = "okay"; +}; + +&otg { + status = "okay"; +}; + &pinctrl { pins_uart2: uart2 { function = "uart2"; |