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| author | Al Cooper <alcooperx@gmail.com> | 2012-07-13 16:44:51 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-10-11 11:04:34 +0200 |
| commit | da4b62cd6762ce327f660c6e45c8d5a739197159 (patch) | |
| tree | 7cbb0b1ce047c514f92da5ef382ca0bc6002cf21 /arch/mips/include/asm/cpu.h | |
| parent | c5600b2dd9fc7318feddf69f127ca793437c714d (diff) | |
| download | linux-stable-da4b62cd6762ce327f660c6e45c8d5a739197159.tar.gz linux-stable-da4b62cd6762ce327f660c6e45c8d5a739197159.tar.bz2 linux-stable-da4b62cd6762ce327f660c6e45c8d5a739197159.zip | |
MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)
The PCI (Program Counter Interrupt) bit in the "cause" register
is mandatory for MIPS32R2 cores, but has also been added to some R1
cores (BMIPS5000). This change adds a cpu feature bit to make it
easier to check for and use this feature.
Signed-off-by: Al Cooper <alcooperx@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/4106/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/cpu.h')
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 554e2d29965d..7dc0db8b9426 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -320,7 +320,8 @@ enum cpu_type_enum { #define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ -#define MIPS_CPU_RIXI 0x00400000 /* CPU has TLB Read/eXec Inhibit */ +#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ +#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ /* * CPU ASE encodings |