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| author | Kelvin Cheung <keguang.zhang@gmail.com> | 2012-10-23 05:17:00 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2012-11-09 11:37:20 +0100 |
| commit | 17ded0a89b3b0b6ac626d58d469ef899f21e2d42 (patch) | |
| tree | 6db9edc67a722d391c7ae3dfc4796b60d02d63e1 /arch/mips/include/asm | |
| parent | ed21cfe207276e2d2883173399dd0380db372e18 (diff) | |
| download | linux-stable-17ded0a89b3b0b6ac626d58d469ef899f21e2d42.tar.gz linux-stable-17ded0a89b3b0b6ac626d58d469ef899f21e2d42.tar.bz2 linux-stable-17ded0a89b3b0b6ac626d58d469ef899f21e2d42.zip | |
MIPS: Loongson1B: use common clock infrastructure instead of private APIs
Use common clock infrastructure instead of private APIs.
1. Enable COMMON_CLK in the Kconfig.
2. Remove private clock APIs, which are replaced by the code in
drivers/clk/clk-ls1x.c.
3. Modify header file for drivers/clk/clk-ls1x.c.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4431
Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/mach-loongson1/platform.h | 1 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-loongson1/regs-clk.h | 7 |
2 files changed, 5 insertions, 3 deletions
diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h index 2f171617bade..f584017eb8a7 100644 --- a/arch/mips/include/asm/mach-loongson1/platform.h +++ b/arch/mips/include/asm/mach-loongson1/platform.h @@ -18,6 +18,7 @@ extern struct platform_device ls1x_eth0_device; extern struct platform_device ls1x_ehci_device; extern struct platform_device ls1x_rtc_device; +extern void __init ls1x_clk_init(void); void ls1x_serial_setup(void); #endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */ diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h index 8efa7fb9f73a..a81fa3d0dc91 100644 --- a/arch/mips/include/asm/mach-loongson1/regs-clk.h +++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h @@ -20,14 +20,15 @@ /* Clock PLL Divisor Register Bits */ #define DIV_DC_EN (0x1 << 31) -#define DIV_DC (0x1f << 26) #define DIV_CPU_EN (0x1 << 25) -#define DIV_CPU (0x1f << 20) #define DIV_DDR_EN (0x1 << 19) -#define DIV_DDR (0x1f << 14) #define DIV_DC_SHIFT 26 #define DIV_CPU_SHIFT 20 #define DIV_DDR_SHIFT 14 +#define DIV_DC_WIDTH 5 +#define DIV_CPU_WIDTH 5 +#define DIV_DDR_WIDTH 5 + #endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */ |